SBAU411 February   2023 ADS127L21

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 ADS127L21 EVM Kit
    2. 1.2 ADS127L21EVM Board
    3. 1.3 ADS127L21EVM-PDK-GUI Unsupported Features
    4. 1.4 Related Documentation
  4. 2Analog Interface
    1. 2.1 EVM Analog Input Options
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 ADC Input Drive Amplifiers
    4. 2.4 VCOM Buffer
    5. 2.5 Onboard Voltage Reference
    6. 2.6 External Voltage Reference
    7. 2.7 Clock Tree
  5. 3Digital Interface
    1. 3.1 Serial Interface
    2. 3.2 I2C bus for Onboard EEPROM
  6. 4Power Supplies
    1. 4.1 Power Connection and Configuration
    2. 4.2 Low Dropout Regulator (LDO)
  7. 5ADS127L21 EVM Software Installation
  8. 6EVM Operation
    1. 6.1 Connecting the Hardware
    2. 6.2 Optional EVM Connections
    3. 6.3 EVM GUI Global Settings for ADC Control
    4. 6.4 Time Domain Display
    5. 6.5 Frequency Domain Display
    6. 6.6 Histogram Display
    7. 6.7 Digital Filter Configuration
    8. 6.8 Digital Filter Response
  9. 7Bill of Materials, Schematics, and Layout
    1. 7.1 Bill of Materials
    2. 7.2 Schematics
    3. 7.3 Board Layout

6.7 Digital Filter Configuration

The Digital Filter Configuration page allows loading of custom digital filters into both the FIR and IIR programmable filter registers inside the ADS127L21 ADC. These filters are designed in separate tools, such as MATLAB®, and the coefficients can be viewed and transferred to the ADS127L21 filter registers. There are several options to enable or disable different filter stages inside the ADS127L21; see the ADS127L21 data sheet for details. As shown in #GUID-84B4427D-0752-4294-B66C-EFA76E7CB64C, the Filter Sequence, Selection, and Type can be selected. FIR and IIR coefficient files can also be loaded and the values can be viewed.

GUID-20230125-SS0I-HW99-F4ND-MZQZJ5JLHGTX-low.png Figure 6-8 Digital Filter Configuration