SBAU411 February   2023 ADS127L21

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 ADS127L21 EVM Kit
    2. 1.2 ADS127L21EVM Board
    3. 1.3 ADS127L21EVM-PDK-GUI Unsupported Features
    4. 1.4 Related Documentation
  4. 2Analog Interface
    1. 2.1 EVM Analog Input Options
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 ADC Input Drive Amplifiers
    4. 2.4 VCOM Buffer
    5. 2.5 Onboard Voltage Reference
    6. 2.6 External Voltage Reference
    7. 2.7 Clock Tree
  5. 3Digital Interface
    1. 3.1 Serial Interface
    2. 3.2 I2C bus for Onboard EEPROM
  6. 4Power Supplies
    1. 4.1 Power Connection and Configuration
    2. 4.2 Low Dropout Regulator (LDO)
  7. 5ADS127L21 EVM Software Installation
  8. 6EVM Operation
    1. 6.1 Connecting the Hardware
    2. 6.2 Optional EVM Connections
    3. 6.3 EVM GUI Global Settings for ADC Control
    4. 6.4 Time Domain Display
    5. 6.5 Frequency Domain Display
    6. 6.6 Histogram Display
    7. 6.7 Digital Filter Configuration
    8. 6.8 Digital Filter Response
  9. 7Bill of Materials, Schematics, and Layout
    1. 7.1 Bill of Materials
    2. 7.2 Schematics
    3. 7.3 Board Layout

2.7 Clock Tree

#GUID-E4618236-AF03-4089-A4A3-9FC32077E599 shows the different clock options for the ADS127L21EVM. The default position for jumper (JP7) 2-3 routes the PHI digital controller board clock to the CLK pin on the ADS127L21 (U3). If the ADS127L21EVM is used without the PHI board, then change the shunt on jumper (JP7) to position 1-2 to directly route the local clock to ADS127L21 (U3). Jumper (JP6) 2-3 enables the local 32.768-MHz oscillator (Y1) on the ADS127L21EVM board, or if inactive (JP6) 1-2, allows an external clock supplied on the SMA connector (J14). The default position for jumper (JP6) 2-3 selects the local 32.768-MHz oscillator (Y1). The ADS127L21EVM-PDK-GUI software by default uses the 32.768-MHz (Y1) oscillator, but can also select the 24-MHz PHI clock source. If an external clock source is used, jumper (JP6) 1-2 position, use a CMOS square-wave signal with an amplitude equal to IOVDD (2.5 V when using the PHI board) and a frequency within the specified range of the ADS127L21.

Figure 2-6 Clock Tree