SBAU417A July   2025  – September 2025 AFE7952

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Recommended Test Environment
    2. 2.2 Required Hardware
    3. 2.3 Hardware Setup
      1. 2.3.1 AFE7952 EVM and TSW14J58 EVM Connections
      2. 2.3.2 Power Supply Setup
  7. 3Software
    1. 3.1 Required Software
      1. 3.1.1 Software Installation Sequence
    2. 3.2 Latte Overview
      1. 3.2.1 Latte User Interface
      2. 3.2.2 Useful Latte Short-Cuts
  8. 4Implementation Results
    1. 4.1 AFE7952EVM Configuration
      1. 4.1.1 Connect Latte to Board
      2. 4.1.2 Compile Libraries
      3. 4.1.3 Program AFE7952 EVM
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
    2. 4.2 AFE7952EVM Configuration Modifications
      1. 4.2.1 Data Converter Clocks Settings
      2. 4.2.2 Data Rate and JESD Parameters
      3. 4.2.3 Steps to Modify NCO
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Status Check and Troubleshooting Guidelines
      1. 6.1.1 AFE7952 EVM Status Indicators
      2. 6.1.2 TSW14J58 EVM
    2. 6.2 Trademarks
  11. 7Revision History

4.2 AFE7952EVM Configuration Modifications

The provided scripts configure the AFE7952 with the default settings declared in Latte scripts. Change the settings by modifying a set of parameters.

This section includes the sequence of steps to modify the bring-up for the AFE7952EVM through the python scripts. The example used in this section is the default AFE7952EVM. Table 4-1 shows the default mode configuration overview.

Table 4-1 AFE7952 EVM Default Configuration Overview
ModeDefault Programming
TX (transmitter)4 TXDACs are enabled, DSA = 0, LMFSHd_2TX = 44210, 24 × interpolation, 491.52MSPS data rate
RX (receiver)4 RXADCs are enabled, DSA = 0, LMFSHd_2RX = 24410, 12 × decimation, 245.76MSPS data rate
FBRX (feedback receiver)2 FBADCs are enabled, DSA = 0, LMFSHd_1FB = 22210, 6 × decimation, 491.52MSPS data rate
SerDes8 lanes running at 9830.4Mbps
Data Converter Clock RatesFRXADC = 2949.12MSPS, FFBADC = 2949.12MSPS, FTXDAC = 11796.4MSPS
StatusRX AGC is disabled, RX, TX DSA step impairments are uncorrected, DAC is in interleaved mode