SBAU417A July   2025  – September 2025 AFE7952

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Recommended Test Environment
    2. 2.2 Required Hardware
    3. 2.3 Hardware Setup
      1. 2.3.1 AFE7952 EVM and TSW14J58 EVM Connections
      2. 2.3.2 Power Supply Setup
  7. 3Software
    1. 3.1 Required Software
      1. 3.1.1 Software Installation Sequence
    2. 3.2 Latte Overview
      1. 3.2.1 Latte User Interface
      2. 3.2.2 Useful Latte Short-Cuts
  8. 4Implementation Results
    1. 4.1 AFE7952EVM Configuration
      1. 4.1.1 Connect Latte to Board
      2. 4.1.2 Compile Libraries
      3. 4.1.3 Program AFE7952 EVM
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
    2. 4.2 AFE7952EVM Configuration Modifications
      1. 4.2.1 Data Converter Clocks Settings
      2. 4.2.2 Data Rate and JESD Parameters
      3. 4.2.3 Steps to Modify NCO
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Status Check and Troubleshooting Guidelines
      1. 6.1.1 AFE7952 EVM Status Indicators
      2. 6.1.2 TSW14J58 EVM
    2. 6.2 Trademarks
  11. 7Revision History

1.1 Introduction

The AFE7952 devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrates phase-locked loop (PLL) and voltage-controlled oscillator (VCO) for generating data converter clocks. The AFE7952 device integrates eight JESD204B- and JESD204C-compatible serializer and deserializer (SerDes) transceivers capable of running up to 29.5Gbps to transmit and receive digital data through the onboard FPGA mezzanine card (FMC) connector.

This document is the user's guide for the evaluation board (EVMs) meant for evaluating the AFE7952 integrated RF sampling transceiver from Texas Instruments. This user's guide describes the basic steps and functions that are required for the proper operation and quick setup of the EVM. The AFE7952EVM includes a clocking and power solution and runs off a single 5.5V supply. As AFE7952EVM Top View shows, the RF inputs and outputs using subminiature version A (SMA) connectors are on the top side of the EVM. A reference clock (for example, 10MHz) to lock the onboard voltage-controlled crystal oscillator (VCXO) with the LMK04828, PLL-1 can be provided to the connector named LMK CLKIN (SMA J19).

Note: Many typical lab equipments have a 10MHz oscillator output to synchronize multiple lab systems. The onboard LMK04828 can accept the 10MHz from external lab equipment to establish synchronization and coherency of the data capture and generation to the AFE7952 EVM.

SMA J12 (REF_CLK_HIGH) or SMA J13 (REF_CLK_LOW) can be used to feed an external reference clock to lock the PLLs in the AFE7952. The USB connector and the 5.5V connector are on the right side of the board.

Figure 1-1 shows the bottom view of the AFE7952EVM.

AFE7952EVM AFE7952EVM Bottom View Figure 1-1 AFE7952EVM Bottom View

The capture card used with the AFE7952 EVM is the TSW14J58. TSW14J58 supports a SerDes speed of up to 29.5Gbps. Refer to Figure 1-2 for typical the connections between the TSW14J58 EVM and the AFE7952 EVM.

AFE7952EVM AFE7952EVM and TSW14J58EVM Rev. A10 Figure 1-2 AFE7952EVM and TSW14J58EVM Rev. A10