SBOSAN2A August   2025  – December 2025 PGA854

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Control
      2. 7.3.2 Input Protection
      3. 7.3.3 Output Common-Mode Pin
      4. 7.3.4 Using the Fully Differential Output Amplifier to Shape Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Linear Operating Input Range
      2. 8.1.2 Current Consumption with Differential Inputs
    2. 8.2 Typical Application
      1. 8.2.1 ADS127L11 and ADS127L21B, 24-Bit, Delta-Sigma ADC Driver Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS = VSOUT = ±15V, VICM = VOCM at mid-supply, RL = 10kΩ, and G = 1V/V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Differential offset voltage (RTI) G = 5 to 100 ±50 ±300 µV
G = 0.5, 1, 2 ±100 / G ±700 / G
Differential offset voltage drift (RTI) TA = –40°C to +125°C G > 1 ±0.1 ±1.0 µV/°C
G = 0.5, 1 ±0.2 ±2.0
PSRR Power-supply rejection ratio ±4.5V ≤ VS ≤ ±18V, RTI G = 0.5 108 124 dB
G = 1 114 128
G = 2 118 130
G ≥ 5 120 134
zid Differential input impedance 100 || 1 GΩ || pF
TA = –40°C to +125°C 10 || 1
zic Common-mode input impedance 100 || 4.4
VICM Common-mode input voltage VS = ±4.5V to ±18V, TA = –40°C to +125°C (VS–) + 3 (VS+) – 3 V
VIN Differential input voltage(1) –16 +16 V
CMRR Common-mode rejection ratio At dc to 60Hz,
VICM = ±10V,
TA = –40°C to +125°C,
RTI		 G = 0.5 69 82 dB
G = 1 75 88
G = 2 80 94
G = 5 88 100
G = 10 95 106
G = 20 100 112
G = 50 108 116
G = 100 116 124
BIAS CURRENT
IB Input bias current ±0.5 ±2 nA
TA = –40°C to +125°C ±1 ±3.6
Input bias current drift TA = –40°C to +125°C ±5 pA/°C
IOS Input offset current ±0.5 ±1 nA
TA = –40°C to +125°C ±1 ±2
Input offset current drift TA = –40°C to +125°C ±5 pA/°C
NOISE VOLTAGE
eNI Voltage noise density (RTI) f = 1kHz G = 100 8.5 nV/√Hz
G = 50 8.5
G = 20 8.8
G = 10 8.8
G = 5 10.5
G =2 20
G =1 40
G = 0.5 80
ENI Voltage noise (RTI) fB = 0.1Hz to 10Hz G = 100 0.28 µVPP
G = 50 0.28
G = 20 0.30
G = 10 0.30
G = 5 0.30
G =2 0.41
G =1 0.76
G = 0.5 1.50
iN Input current noise density f = 1kHz 0.2 pA/√Hz
IN Input current noise fB = 0.1Hz to 10Hz 7.9 pAPP
GAIN
G Differential gain 0.5 100 V/V
GE Differential gain error G = 0.5, 1, 2 ±0.005 ±0.035 %
G = 5, 10, 20, 50 ±0.015 ±0.045
G = 100 ±0.025 ±0.055
Differential gain drift TA = –40°C to +125°C G = 2 ±0.05 ±1 ppm/°C
G ≠ 2 ±0.2 ±2
Differential gain nonlinearity G = 0.5, VOUT = 8V
G = 1 to 20, VOUT = 10V		 ±4 ±5.5 ppm
G = 50, 100, VOUT = 10V ±9 ±20
TA = –40°C to +125°C,
G = 0.5, VOUT = 8V
G = 1 to 100, VOUT = 10V		 G ≤ 20 ±5 ±7
G = 50, 100 ±12 ±30
OUTPUT
VO Single-ended output voltage No load, VSOUT = ±2.25V VLVSS + 0.1 VLVDD – 0.1 V
RL = 10kΩ VSOUT = ±2.25V VLVSS + 0.2 VLVDD – 0.2
VSOUT = ±18V VLVSS + 0.4 VLVDD – 0.4
VOUT Differential output voltage VICM and VIN in valid linear operating range(2) G × VIN V
CL Differential load capacitance  Stable operation for differential load 50 pF
ISC Short-circuit current Continuous to VSOUT / 2 ±45 mA
TA = –40°C to +125°C ±20 ±60
FREQUENCY RESPONSE
BW Bandwidth, –3dB G < 10 6.2 MHz
G = 10, 20 5.0
G = 50, 100 2.4
SR Slew rate G = 0.5, VOUT = 8V
G = 1 to 100, VOUT = 10V		 45 V/µs
tS Settling time G = 0.5, VIN = 10V step or
G= 1 to 20, VOUT = 10V step		 To 0.01% 0.75 µs
To 0.0015% 0.9 µs
G = 50
VOUT = 10V step		 To 0.01% 1.3 µs
To 0.0015% 1.4 µs
G = 100
VOUT = 10V step		 To 0.01% 2 µs
To 0.0015% 2.3 µs
Gain switching time 1.5 µs
THD+N Total harmonic distortion and Noise Differential input, f = 10kHz, VOUT = 10VPP –99 dB
Single-ended input, f = 10kHz, VOUT = 10VPP –93
HD2 Second-order harmonic distortion Differential input, f = 10kHz, VOUT = 10VPP –121 dB
Single-ended input, f = 10kHz, VOUT = 10VPP –112
HD3 Third-order harmonic distortion Differential input, f = 10kHz, VOUT = 10VPP –105 dB
Single-ended input, f = 10kHz, VOUT = 10VPP –104
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
VOCM Output common-mode control voltage(3) VS = ±4.5V VLVSS + 1.5 VLVDD – 1.5 V
VS = ±18V VLVSS + 2 VLVDD – 2
Small-signal bandwidth VOCM pin VOCM = 100mVPP 14 MHz
Large-signal bandwidth VOCM pin VOCM = 0.6VPP 14 MHz
DC output balance(4) VOCM fixed at mid-supply (VOUT = ±1V) 95 dB
Input impedance VOCM pin 250 || 1 kΩ || pF
VOUTCM offset from mid-supply VOCM pin floating ±1 ±4.5 mV
VOUTCM offset voltage(5) VOCM = VICM, VOUT = 0V ±1 ±4.5 mV
VOUTCM offset voltage drift VOCM = VICM, VOUT = 0V, TA = –40°C to +125°C ±20 ±40 µV/°C
INPUT STAGE POWER SUPPLY
IQ_input Input stage quiescent current
VS+, VS–		 VIN = 0V, VICM = 0V 3.2 3.9 mA
TA = –40°C to +125°C 4.9
OUTPUT STAGE POWER SUPPLY
IQ_output Output stage quiescent current
LVDD, LVSS		 VIN = 0V, VOCM fixed at mid-supply 2.3 2.8 mA
TA = –40°C to +125°C 3.5
DIGITAL LOGIC
VIL Digital input logic low A0, A1, A2 pins, referred to DGND VDGND VDGND + 0.8 V
VIH Digital input logic high A0, A1, A2 pins, referred to DGND VDGND + 1.8 VS+ V
Digital input pin current A0, A1, A2 pins 1.5 3 µA
VDGND DGND voltage VS– (VS+) – 4 V
DGND reference current 4 10 µA
(1) Differential Input voltage of the PGA854 amplifier (VIN = VIN+ – VIN–). The valid input range depends on input common-mode voltage VICM, gain G, and output common-mode voltage VOCM. See Section 8.1.1.
(2) Differential output voltage VOUT = VOUT+ - VOUT– See Section 8.1.1 for valid linear operating range of the amplifier.
(3) VOCM is the Voltage on VOCM pin. Actual output common-mode voltage is calculated from single-ended output voltages VOUTCM = (VOUT+ + VOUT–) / 2.
(4) DC output balance is defined as |VOUTCM(at VIN = +1) – VOUTCM(at VIN = –1)| / 2.
(5) VOUTCM offset voltage is defined as VOUTCM – VOCM.