SCASE78A April   2025  – September 2025 TPUL2G123-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   5
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 State Machine Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Retriggerable One-Shot
      3. 7.3.3 Timing Mechanism and Accuracy
      4. 7.3.4 Balanced CMOS Push-Pull Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Partial Power Down (Ioff)
      8. 7.3.8 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Edge Detector
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Timing Components
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application - Delayed Pulse Generator
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

8.2.2 Detailed Design Procedure

Texas Instruments provides an Excel-based calculator for getting the best results when using the TPUL2G123-Q1. This calculator can be found through the device's product folder, located in the Design and development section. The steps below are used for manually calculating the required timing component values using the information available in this document.

  1. Select the desired output pulse width, which will be referred to as two.
  2. Solve: Cext1 = two/50000.
  3. Select the nearest decade capacitor value to Cext1 from the following and use for Cext. { 100pF, 1nF, 10nF, 100nF, 1µF, 10µF }
  4. Solve: Rext1 = two/Cext.
  5. Using Rext1 from step 4 and Cext from step 3, find the closest K factor using the appropriate plot from the Typical Characteristics section.
  6. Solve: Rext = two/(K × Cext)
  7. Connect the selected timing resistor, Rext, from RC to VCC.
  8. Connect the selected timing capacitor, Cext, from RC (positive) to C (negative). The C pin can additionally be connected to ground, however it is not required for normal operation.
  9. Add a 0.1µF bypass capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section.
  10. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit, however, it will optimize performance and prevent reliability issues. This can be accomplished by providing short, appropriately sized traces from the TPUL2G123-Q1 to any receiving devices.
  11. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously.
  12. Thermal issues are rarely a concern for TPUL family devices, however, the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.