SCAU061 August   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 CDCLVP111-SEP Clock Mux Selection
    2. 2.2 CDCLVP111-SEP EVM Input Biasing
    3. 2.3 CDCLVP111-SEP EVM Output Termination
    4. 2.4 Assembly Instructions
      1. 2.4.1 CDCLVP111-SEP Setup and Quick Test
        1. 2.4.1.1 Power Supply Setup
  8. 3Hardware Design Files
    1. 3.1 CDCLVP111-SEP EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)

1.1 Introduction

The CDCLVP111-SEP EVM is designed for evaluating the CDCLVP111-SEP. The CDCLVP111-SEP is a 1 to 10 LVPECL buffer with selectable input. The evaluation setup is shown in Figure 1-1. The evaluation setup is essentially a break-out board exposing full functionality of the device with flexible input and output-biasing options.

This user’s guide provides an overview of the evaluation module (EVM) including hardware features to be considered while using this module. This manual is applicable to the CDCLVP111-SP EVM which is synonymous with CDCLVP111EVM-CVAL, the orderable part number. The EVM provides a platform for evaluating the clock buffer under various voltage and bias configurations.

CDCLVP111SEPEVM CDCLVP111-SEP EVM Block DiagramFigure 1-1 CDCLVP111-SEP EVM Block Diagram