SCAU061 August   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 CDCLVP111-SEP Clock Mux Selection
    2. 2.2 CDCLVP111-SEP EVM Input Biasing
    3. 2.3 CDCLVP111-SEP EVM Output Termination
    4. 2.4 Assembly Instructions
      1. 2.4.1 CDCLVP111-SEP Setup and Quick Test
        1. 2.4.1.1 Power Supply Setup
  8. 3Hardware Design Files
    1. 3.1 CDCLVP111-SEP EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)

2.3 CDCLVP111-SEP EVM Output Termination

The CDCLVP111-SEP EVM is configured with no on-board output termination installed for CLK[5:0] by default. This allows simple connection to 50Ω terminated test equipment. There are 0402 pads for 50Ω terminations on board. This allows the connection of a high-impedance or differential probe. Simply install the pair of resistors on the pads of the outputs being evaluated. In Figure 2-2, install R30 and R33 for on-board termination. Leave them unconnected for direct termination to 50Ω test equipment. CLK[4:0] have on board 50Ω terminations along with AC coupling capacitors, which can allow for those outputs to be connected directly to a phase noise analyzer.

CDCLVP111SEPEVM On Board Optional Output TerminationFigure 2-2 On Board Optional Output Termination