SCAU061 August   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 CDCLVP111-SEP Clock Mux Selection
    2. 2.2 CDCLVP111-SEP EVM Input Biasing
    3. 2.3 CDCLVP111-SEP EVM Output Termination
    4. 2.4 Assembly Instructions
      1. 2.4.1 CDCLVP111-SEP Setup and Quick Test
        1. 2.4.1.1 Power Supply Setup
  8. 3Hardware Design Files
    1. 3.1 CDCLVP111-SEP EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)

2.4.1 CDCLVP111-SEP Setup and Quick Test

The CDCLVP111-SEP EVM is designed to ease lab-based evaluation by utilizing an offset LVPECL bias point set to earth ground. This allows two power supplies to easily connect the outputs to standard 50Ω terminated test equipment. Utilizing two supplies provides the proper termination for LVPECL drivers. The EVM also provides pads near SMA jacks for on-board 50Ω termination for cases that require using high-impedance probes.