SCAU061 August   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 CDCLVP111-SEP Clock Mux Selection
    2. 2.2 CDCLVP111-SEP EVM Input Biasing
    3. 2.3 CDCLVP111-SEP EVM Output Termination
    4. 2.4 Assembly Instructions
      1. 2.4.1 CDCLVP111-SEP Setup and Quick Test
        1. 2.4.1.1 Power Supply Setup
  8. 3Hardware Design Files
    1. 3.1 CDCLVP111-SEP EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)

2.2 CDCLVP111-SEP EVM Input Biasing

The CDCLVP111-SEP EVM is designed to allow implementation of flexible input biasing. By default, the board is configured with two 50Ω resistors to LVPECL bias level (VCC-2 V, earth ground) for both CLK inputs. This configuration allows for direct use of LVPECL drivers.

CDCLVP111SEPEVM Input Biasing SchematicFigure 2-1 Input Biasing Schematic

The board also is designed to allow AC-coupled LVDS inputs. This is accomplished by the by having the LVDS input signal AC coupled with the corresponding 50Ohm to GND termination populated on both intra-pairs of CLKx pins.

The final termination option is to allow single-ended input to drive CLKx. A few 0Ω resistors, R8,R10,R14,R17, can be added to the circuit to connect VBB output to the unused pin of CLKx.