2 Guarding Best Practices

To ensure the highest level of leakage performance, there are some best practices for guarding that should be adhered to. As mentioned earlier, the first barrier that needs to be protected again is surface contamination that can often lead to stray leakage currents. In order to counteract this, it is best to bury sensitive nets within the PCB itself to reduce the possibility of any type of debris or contamination from providing leakage paths to the sensitive nets. To go even further, the next recommendation would be to implement a “boxing” ring around the entire net. What this means is that in addition to the traditional guarding which is just on the same layer as the net, the layers above and below also provide shielding by being at the same potential as the guard traces. This type of configuration will mimic the effects of a shielding cable in which it shields the net 360°. Figure 2-1 provides a visual representation.

With package sizes becoming smaller and smaller, this can introduce challenges in incorporating a full guard ring on the trace due to the pitch of some packages. To address this, the designer will need to run the guard ring and traces as close to the pin as possible while still leaving some space between the adjacent guard traces (see Figure 2-2).

However, if a full guard is required, TI does offer devices that are more guarding friendly in SOIC packages. These are wider pitch devices which will allow for a full guard to be implemented around each pin of the device. One such example can be seen using the MUX36S16DWR, as shown in Figure 2-3.

Lastly, the design must ensure that the guard is well generated. What this means is that the guard voltage mimics the net voltage as closely as possible to provide the optimal guarding results. To do this, one must just simply incorporate a precision buffer to be able to drive the guard appropriately. Figure 2-4 illustrates a sample topology.

This topology is recommended to be designed with a precision buffer to reduce any extra leakage currents emanating from the op-amp itself and to ensure the closest guard possible. Table 2-1 shows some recommended op-amps to use for this application.