Serial peripheral interface (SPI) provides synchronous communication between a processor and peripheral. SPI is a four line “controller-peripheral” architecture communication interface, with three lines driven by the controller (usually the processor) and one line driven by the peripheral (usually the peripheral). Table 2-1 describes the SPI signal interface.
|CLK||Clock Signal||Controller to Peripheral|
|CIPO||Controller Input/Peripheral Output||Peripheral to Controller|
|COPI||Controller Output/Peripheral Input||Controller to Peripheral|
|CS||Peripheral Select||Controller to Peripheral|
The first signal line driven by the controller is CLK, which is the clock signal. With each clock pulse, the controller can transmit or receive one bit to or from the peripheral. The data rate is usually 10 Mbps, however, it can be extended as desired in the system. Since SPI is full duplex, two data lines are needed: COPI and CIPO. COPI stands for controller output peripheral input, and is driven by the controller to send data to the peripheral. CIPO stands for controller input peripheral output, and is driven by the peripheral to send data to the controller. The final line is CS, which is the peripheral select signal. The CS line is driven low by the controller to select the peripheral device for communication. Multiple peripherals may exist in a system and this ensures that the desired peripheral is being communicated with to prevent any system level bus contention. SPI is commonly used in the following: