SCEA065B November   2018  – March 2021 SN74AVC4T774 , SN74AXC1T45 , SN74AXC4T245 , SN74AXC4T774 , SN74AXC8T245 , SN74AXC8T245-Q1 , SN74AXCH1T45 , SN74AXCH4T245 , SN74AXCH8T245

 

  1.   Trademarks
  2. 1Introduction
  3. 2Common Interfaces and AXC Implementation
    1. 2.1 General Purpose Input Output (GPIO)
    2. 2.2 Serial Peripheral Interface (SPI)
      1. 2.2.1 Voltage Translation for SPI
      2. 2.2.2 SPI Applications
    3.     8
    4. 2.3 UART
      1. 2.3.1 Voltage Translation With UART
      2. 2.3.2 UART Applications
    5. 2.4 Joint Test Action Group (JTAG)
      1. 2.4.1 JTAG Applications
    6. 2.5 Reduced Gigabit Media Independent Interface (RGMII)
      1. 2.5.1 Voltage Translation for RGMII
      2. 2.5.2 RGMII Applications
      3. 2.5.3 Skew Performance
  4. 3Summary
  5. 4Related Documentation
  6. 5Revision History

2.5 Reduced Gigabit Media Independent Interface (RGMII)

Reduced Gigabit Media Independent Interface (RGMII) is a high speed interface to connect a media access control device (MAC) to an Ethernet physical layer chip (PHY). It is a modification of Media Independent Interface (MII), with the improvements being the gigabyte data rate, as opposed to 100 Mbps, and reduced interface pin count.

Table 2-3 RGMII Signals
SIGNAL DESCRIPTION DIRECTION
TXCClock signalMAC to PHY
TXD[0…3]Transmitted DataMAC to PHY
TX_CTLTransmitter Enable/ErrorMAC to PHY
RXCRecovered clock signal (from received data)PHY to MAC
RXD[0…3]Received DataPHY to MAC
RX_CTLReceived data valid/receiver errorPHY to MAC

RGMII uses 12 lines as described in Table 2-3. The clock is set to 125 MHz for achieving gigabit speeds, and 25/2.5 MHz for 100/10 Mbps speeds, respectively. In gigabit operation, data is clocked on both the rising and falling edge of this signal, and in 100/10 Mbps operation, data is clocked only on the rising edge. Due to the high speed requirements of RGMII, a tight timing budget must be implemented with limited skew. The final two signals are RX_CTL and TX_CTL, two control signals multiplexed by the clock signals. RX_CTL carries the received data valid signal and the receiver error signal. TX_CTL contains the transmitter enable and transmitter error signal.