Reduced Gigabit Media Independent Interface (RGMII) is a high speed interface to connect a media access control device (MAC) to an Ethernet physical layer chip (PHY). It is a modification of Media Independent Interface (MII), with the improvements being the gigabyte data rate, as opposed to 100 Mbps, and reduced interface pin count.
|TXC||Clock signal||MAC to PHY|
|TXD[0…3]||Transmitted Data||MAC to PHY|
|TX_CTL||Transmitter Enable/Error||MAC to PHY|
|RXC||Recovered clock signal (from received data)||PHY to MAC|
|RXD[0…3]||Received Data||PHY to MAC|
|RX_CTL||Received data valid/receiver error||PHY to MAC|
RGMII uses 12 lines as described in Table 2-3. The clock is set to 125 MHz for achieving gigabit speeds, and 25/2.5 MHz for 100/10 Mbps speeds, respectively. In gigabit operation, data is clocked on both the rising and falling edge of this signal, and in 100/10 Mbps operation, data is clocked only on the rising edge. Due to the high speed requirements of RGMII, a tight timing budget must be implemented with limited skew. The final two signals are RX_CTL and TX_CTL, two control signals multiplexed by the clock signals. RX_CTL carries the received data valid signal and the receiver error signal. TX_CTL contains the transmitter enable and transmitter error signal.