The SN74AXC8T245-Q1 AEC-Q100 qualified device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, and 3.3 V) and vice versa.
The device operates by using two independent power-supply rails (VCCA and VCCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track VCCB, which accepts any supply voltage from 0.65 V to 3.6 V.
The SN74AXC8T245-Q1 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable (OE) input is used to disable the outputs so the buses are effectively isolated.
The SN74AXC8T245-Q1 device is designed so the control pins (DIR and OE) are referenced to VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
The VCC isolation feature ensures that if either VCC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state.
To ensure the high-impedance state of the level shifter I/Os during power up or power down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
5V version
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74AXC8T245-Q1 Automotive 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs datasheet (Rev. C) | PDF | HTML | 13 Oct 2021 |
| Application note | Translate Voltages for RGMII (Rev. A) | PDF | HTML | 06 Aug 2021 | |
| Selection guide | Voltage Translation Buying Guide (Rev. A) | 15 Apr 2021 | ||
| Application note | Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) | PDF | HTML | 29 Mar 2021 | |
| Application note | Glitch free power sequencing with AXC level translators (Rev. A) | 20 Sep 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.
The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)
| Package | Pins | Download |
|---|---|---|
| TSSOP (PW) | 24 | View options |
| VQFN (RGY) | 24 | View options |
| VQFN (RHL) | 24 | View options |
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