SN74AXC8T245-Q1

• AEC-Q100 Qualified for automotive applications
• Qualified fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
• Operating temperature from –40°C to +125°C
• Multiple direction-control pins to allow simultaneous up and down translation
• Up to 380 Mbps support when translating from 1.8 V to 3.3 V
• V_CC isolation feature to effectively Isolate both bses in a power-down scenario
• Partial power-down mode to limit backflow current in a power-Down scenario
• Compatible with SN74AVC8T245-Q1 level shifter
• Latch-up performance exceeds 100 mA per JESD 78, Class II

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The SN74AXC8T245-Q1 AEC-Q100 qualified device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, 3.3 V) and vice versa.

The device operates by using two independent power-supply rails (V_CCA and V_CCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track V_CCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track V_CCB, which accepts any supply voltage from 0.65 V to 3.6 V.

The SN74AXC8T245-Q1 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable (OE) input is used to disable the outputs so the buses are effectively isolated.

The SN74AXC8T245-Q1 device is designed so the control pins (DIR and OE) are referenced to V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The V_CC isolation feature ensures that if either V_CC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state.

To ensure the high-impedance state of the level shifter I/Os during power up or power down, OE should be tied to V_CCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.