The SN74AXCH4T245 is a four-bit noninverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track VCCB, which accepts any supply voltage from 0.65 V to 3.6 V. The SN74AXCH4T245 device is compatible with a single-supply system.
The SN74AXCH4T245 device is designed for asynchronous communication between data buses and transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (1DIR and 2DIR). The output-enable inputs (1OE and 2OE) are used to disable the outputs so the buses are effectively isolated. All control pins (xDIR and xOE) are referenced to VCCA.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. If a supply is present for VCCA or VCCB, the bus-hold circuitry always remains active on the A or B inputs respectively, independent of the state of the direction control or output enable pins.
To ensure the high-impedance state of the level shifter I/Os during power up or power down, the xOE pins should be tied to VCCA through a pullup resistor.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or sourced into an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.
The VCC isolation feature ensures that if either VCCA or VCCB is less than 100 mV, all I/O ports enter a high-impedance state by disabling the outputs.
Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74AXCH4T245 Four-bit bus transceiver with configurable voltage translation, tri-state outputs, and bus-hold inputs datasheet | PDF | HTML | 11 Nov 2016 |
| Application note | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 02 Oct 2024 | |
| Application note | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 12 Jul 2024 | |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 03 Jul 2024 | |
| Selection guide | Voltage Translation Buying Guide (Rev. A) | 15 Apr 2021 | ||
| Application note | Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) | PDF | HTML | 29 Mar 2021 | |
| Application note | Glitch free power sequencing with AXC level translators (Rev. A) | 20 Sep 2018 | ||
| Application note | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 17 Sep 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.
The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| UQFN (RSV) | 16 | Ultra Librarian |
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