3 Are Pullup Resistors Required for Push-Pull Applications with the LSF?

Pullups are needed when used with open-drain interfaces to drive the bus to a logic high state since open-drain drivers are only capable of pulling the bus low. But when LSF is being used with push-pull drivers, this requirement becomes ambiguous.

Figure 3-1 Example Schematic of LSF Used in Both Push-Pull and Open Drain Configurations

Take an example of a down translation use case (A2/ B2 in above schematic) where pullup resistors are recommended on the output (A-side) if excessive leakage current is observed. This happens when the receiver is attempting to draw more current then the internal FET can provide during a logic high state. When this occurs, the voltage on the output side drops due to the internal FET turning on (transition to the linear region) as the source and gate voltage gap become wider (V_GS> V_TH). This in turn pulls the bus low and result in a false logic low signal for the device back upstream. To resolve this, external pullups are used to offset the leakage so that the FET can remain in the cutoff state (V_GS<V_TH) during a transmitted logic high signal. In the below Down Translation simulations, a leakage current at the output is imitated and the VOH levels are measured and compared to VOH levels if pullups were used in place.

Simulation #1: Effect of excessive leakage current on receiver side during down translation.

In Figure 3-2, we use a current source at the output side (IG1) to simulate a leakage path on the receiver side. The step function of the current at IG1 increases linearly and the voltage at the output is measured.

Figure 3-2 Simulation Setup With Excessive Leakage on Receiver Side

Figure 3-3 Simulation Result With Excessive Leakage on Receiver Side

As output leakage current (IG1) increased, the observed output voltage begins to sag further until the output voltage drifts below the threshold voltage. By now, the difference at the output and the gate voltage becomes large enough that the low side (A-side) becomes the source, thus the FET transitioning back into linear region. Once the FET is operating in the linear region, the pullup on B-side (input side) begins to source current into the A side, where the downward slope can be modeled as V_G- V_TH/ R_PUB. Note here that the data shown in the simulation is only to demonstrate the behavior of the device in this environment. Real life behavior of the device is dependent on multiple factors (process, variation, temperature, and others) so there is no guarantee for the voltage sag to be this small across the leakage current parameters.

Simulation #2: Benefit of having a pullup resistor (2.2kΩ) on receiver side with excessive leakage current on receiver side:

Figure 3-4 Simulation Setup With Excessive Leakage and Pullup Resistor on Receiver Side

Simulation #2: Output level on low-side with external uullup on A-side (2.2kΩ)

Figure 3-5 Simulation #2 Results

Note: Values are taken from simulation only to demonstrate the behavior of leakage current and effect on output voltage with and without pullup resistor used on output.

In the 2nd schematic/ simulation, an external pullup resistor on A side (R_PUA) can be used to help regulate the voltage by sourcing the current which the device on A-side is capable of sinking/ sourcing.