A differential line receiver commonly has a failsafe circuit to prevent the output from switching on input noise. Current LVDS failsafe implementation require either external components with subsequent reductions in signal quality or integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the limitations seen in present solutions. A detailed theory of operation is presented in the Active Fail-Safe in TI’s LVDS Receivers application note.

Figure 8-3 shows one receiver channel with active failsafe, which consists of a main receiver that can respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and the comparator detects when the input differential falls below 80mV. A 600ns failsafe timer filters the window comparator outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.

Figure 8-3 Receiver with active failsafe