SGLS423A February   2025  – December 2025 SN55LVRA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Receiver Output States
      2. 7.3.2 General Purpose Comparator
      3. 7.3.3 Common-Mode Range vs Supply Voltage
    4. 7.4 Equivalent Input and Output Schematic Diagrams
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
      2. 8.2.2 Design Requirements
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Cold Sparing
    3. 8.3 Active Failsafe Feature
    4. 8.4 ECL/PECL-to-LVTTL Conversion with TI's LVDS Receiver
    5. 8.5 Test Conditions
    6. 8.6 Equipment
  10. 9 Power Supply Recommendations
    1. 9.1 Supply Bypass Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Microstrip vs. Stripline Topologies
      2. 10.1.2 Dielectric Type and Board Construction
      3. 10.1.3 Recommended Stack Layout
      4. 10.1.4 Separation Between Traces
      5. 10.1.5 Crosstalk and Ground Bounce Minimization
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

1 Features

  • VID V62/25606-01XE
  • Total ionizing dose characterized at 30krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 50MeV-cm2 /mg
    • Single event transient (SET) characterization report available
  • 400Mbps signaling rate
  • Operates with a single 3.3V supply
  • –4V to 5V extended common-mode input voltage range
  • Differential input thresholds < ±50mV with 50mV of hysteresis over entire common-mode input voltage range
  • Complies with TIA/EIA-644 (LVDS)
  • Active fail-safe assures a high-level output with no input and input remains high-impedance on power down
  • Bus-pin ESD protection exceeds 15kV HBM
  • TTL control inputs are 5V tolerant
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold wire, NiPdAu lead finish
    • One assembly and test site, one fabrication site
    • Extended product life cycle
    • Military (–55°C to 125°C) temperature range
    • Product traceability
    • Meets NASA ASTM E595 outgassing specification