SGLS423A February   2025  – December 2025 SN55LVRA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Receiver Output States
      2. 7.3.2 General Purpose Comparator
      3. 7.3.3 Common-Mode Range vs Supply Voltage
    4. 7.4 Equivalent Input and Output Schematic Diagrams
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
      2. 8.2.2 Design Requirements
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Cold Sparing
    3. 8.3 Active Failsafe Feature
    4. 8.4 ECL/PECL-to-LVTTL Conversion with TI's LVDS Receiver
    5. 8.5 Test Conditions
    6. 8.6 Equipment
  10. 9 Power Supply Recommendations
    1. 9.1 Supply Bypass Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Microstrip vs. Stripline Topologies
      2. 10.1.2 Dielectric Type and Board Construction
      3. 10.1.3 Recommended Stack Layout
      4. 10.1.4 Separation Between Traces
      5. 10.1.5 Crosstalk and Ground Bounce Minimization
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT1 Positive-going differential input voltage threshold VIB = -4V or 5V, VCC = 3.0V to 3.6V, See Figure 6-2 90 mV
VIT2 Negative-going differential input voltage
threshold		 -90
VIT3 Differential input failsafe voltage threshold VCC = 3.0V to 3.6V See Figure 6-2 and Figure 6-5 -32 -100 mV
VID(HYS) Differential input voltage hysteresis,
VIT1 – VIT2		 VCC = 3.0V to 3.6V
 		 50 mV
VCM_RANGE Input common mode voltage range VCC = 3.0V to 3.6V -4 1.2 5 V
VOH High-level output voltage IOH = –4mA, VCC = 3.0V to 3.6V 2.4 V
VOL Low-level output voltage IOL = 4mA, VCC = 3.0V to 3.6V 0.4 V
ICC Supply current G at VCC, No load, Steady-state VID=200mV/-200mV, VCC = 3.0V to 3.6V 2 16 25 mA
Disable and in deep sleep (Disable for >100us), G at GND, VCC = 3.0V to 3.6V 1.1 6
II Input current
(A or B inputs)		 VI = 0V, Other input open -25 25 µA
II Input current
(A or B inputs)		 VI = 2.4V, Other input open -25 25 µA
II Input current
(A or B inputs)		 VI = –4V, Other input open  -80 80 µA
II Input current
(A or B inputs)		 VI = 5V, Other input open -45 45 µA
IID Differential input current
(IIA – IIB)		 VID = 100 mV, VIC = –4V or 5V -5 5 µA
II(OFF) Power-off input current
(A or B inputs)		 VA or VB = –4V or 5V, VCC = 0V -70 70 µA
II(OFF) Power-off input current
(A or B inputs)		 VA or VB = 0V or 2.4V, VCC = 0V -25 25 µA
VIH High-level input voltage (enables) VCC = 3.0V to 3.6V 2 V
IIH High-level input current (enables) VIH = 2V, VCC 3.0V to 3.6V 15 µA
VIL Low-level input voltage (enables) VCC = 3.0V to 3.6V 0.8 V
IIL Low-level input current (enables) VIL = 0.8V, VCC 3.0V to 3.6V 15 µA
IOZ High-impedance output current -12 12 µA