SGLS423A February   2025  – December 2025 SN55LVRA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Receiver Output States
      2. 7.3.2 General Purpose Comparator
      3. 7.3.3 Common-Mode Range vs Supply Voltage
    4. 7.4 Equivalent Input and Output Schematic Diagrams
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
      2. 8.2.2 Design Requirements
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Cold Sparing
    3. 8.3 Active Failsafe Feature
    4. 8.4 ECL/PECL-to-LVTTL Conversion with TI's LVDS Receiver
    5. 8.5 Test Conditions
    6. 8.6 Equipment
  10. 9 Power Supply Recommendations
    1. 9.1 Supply Bypass Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Microstrip vs. Stripline Topologies
      2. 10.1.2 Dielectric Type and Board Construction
      3. 10.1.3 Recommended Stack Layout
      4. 10.1.4 Separation Between Traces
      5. 10.1.5 Crosstalk and Ground Bounce Minimization
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

12 Revision History

Changes from Revision * (February 2025) to Revision A (December 2025)

  • Added "radiation tolerant" to data sheet titleGo
  • Added VID numberGo
  • Added SET characterization report availability and updated SEL to 50MeVGo
  • Updated data sheet status from Advanced Information to Production Data Go
  • Changed the D (SOIC) Package Size in the Package Information tableGo
  • Added bus pin ESD ratingGo
  • Changed HBM ESD from 2kV to 4kVGo
  • Changed CDM ESD from 750V to 1000VGo
  • Changed ROC VIH max for enable to VCC Go
  • Changed VIT1 and VIT2from 50mV to 90mV Go
  • Changed TPHL max from 8ns to 8.5nsGo
  • Changed TLH min from 1.8ns to 1.3ns, max from 8ns to 7.5nsGo
  • Changed td1 max from 11ns to 16nsGo
  • Changed td2 max from 2µs to 2.5µs and removed min limitGo
  • Changed tSK(p) typical from 200ns to 500nsGo
  • Changed typical tsk(o) from 150ns to 130nsGo
  • Changed max TPHZ from 12ns to 15nsGo
  • Changed Application Diagram to 3.3V supply and add more details on C1 and C2 decoupling capacitorsGo
  • Added link to Bypass Capacitance recommendation sectionGo
  • Added more information decoupling capGo
  • Added NOTE on impact on system performanceGo
DATE REVISION NOTES
February 2025 * Initial Release

Changes from , to , (from Revision () to Revision ())

  • Added "radiation tolerant" to data sheet titleGo
  • Added VID numberGo
  • Added SET characterization report availability and updated SEL to 50MeVGo
  • Changed the D (SOIC) Package Size in the Package Information tableGo
  • Go
  • Added bus pin ESD ratingGo
  • Changed HBM ESD from 2kV to 4kVGo
  • Changed CDM ESD from 750V to 1000VGo
  • Changed ROC VIH max for enable to VCC Go
  • Changed VIT1 and VIT2from 50mV to 90mV Go
  • Changed TPHL max from 8ns to 8.5nsGo
  • Changed TLH min from 1.8ns to 1.3ns, max from 8ns to 7.5nsGo
  • Changed td1 max from 11ns to 16nsGo
  • Changed td2 max from 2µs to 2.5µs and removed min limitGo
  • Changed tSK(p) typical from 200ns to 500nsGo
  • Changed typical tsk(o) from 150ns to 130nsGo
  • Changed max TPHZ from 12ns to 15nsGo
  • Go
  • Go
  • Go
  • Changed Application Diagram to 3.3V supply and add more details on C1 and C2 decoupling capacitorsGo
  • Added link to Bypass Capacitance recommendation sectionGo
  • Go
  • Go
  • Go
  • Added more information decoupling capGo
  • Added NOTE on impact on system performanceGo
  • Go
  • Go
  • Go
  • Go
  • Deleted Evaluating the LVDS EVM (SLLA033) bullet in Related Documentation sectionGo
  • Go