SLASFB9B June   2025  – March 2026 MSPM0H3215 , MSPM0H3216

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3   Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 High Frequency Crystal/Clock
      4. 7.9.4 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagram
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Emulation and Debug
      1. 7.18.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0H321x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA_B
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 Security
    17. 8.17 CRC
    18. 8.18 UART
    19. 8.19 SPI
    20. 8.20 I2C
    21. 8.21 Low-Frequency Sub System (LFSS)
    22. 8.22 RTC_B
    23. 8.23 IWDT_B
    24. 8.24 WWDT
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 DEBUGSS
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.15.1 SPI

over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SPI
fSPI SPI clock frequency MCLK = 32MHz
4.5 < VDD < 5.5V
Peripheral or Controller mode		 16(4) MHz
DCSCK SCK Duty Cycle 40 50 60 %
Controller
tSCLK_H/L SCLK High or Low time  (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns
tCS.LEAD CS lead-time, CS active to clock SPH=0 1 SPI CLOCK  ns
tCS.LEAD CS lead-time, CS active to clock SPH=1 1/2 SPI CLOCK 
tCS.LAG CS lag time, Last clock to CS inactive
SPH=0

 1/2 SPI CLOCK ns
tCS.LAG CS lag time, Last clock to CS inactive SPH=1 1 SPI CLOCK
tCS.ACC CS access time, CS active to PICO data out 1/2 SPI CLOCK ns
tCS.DIS CS disable time, CS inactive to PICO high impedance 1 SPI CLOCK ns
tSU.CI POCI input data setup time (1) delayed sampling enabled 3 ns
tSU.CI POCI input data setup time (1) no delayed sampling 34 ns
tHD.CI POCI input data hold time delayed sampling enabled 23 ns
tHD.CI POCI input data hold time no delayed sampling 0 ns
tVALID.CO PICO output data valid time (2) 10 ns
tHD.CO PICO output data hold time (3) 0 ns
Peripheral
tCS.LEAD CS lead-time, CS active to clock 15 ns
tCS.LAG CS lag time, Last clock to CS inactive 1 ns
tCS.ACC CS access time, CS active to POCI data out 45 ns
tCS.DIS CS disable time, CS inactive to POCI high inpedance 45 ns
tSU.PI PICO input data setup time 15 ns
tHD.PI PICO input data hold time 3 ns
tVALID.PO POCI output data valid time(2) 33 ns
tHD.PO POCI output data hold time(3) 7 ns
(1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled.
(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(3) Specifies how long data on the output is valid after the output changing SCLK clock edge
(4) fSPIclk = 1/2tLO/HI with tLO/HI = max(tVALID,CO + tSU,PI, tSU,CI + tVALID,PO).