SLASFC5A September   2024  – October 2025 TAS2320

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 External Class-H Boost Controller
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3 PAGE 2 Registers

Table 7-49 lists the memory-mapped registers for the PAGE 2 registers. All register offset addresses not listed in Table 7-49 should be considered as reserved locations and the register contents should not be modified.

Table 7-49 PAGE 2 Registers
AddressAcronymDescriptionSection
0hPAGEDevice PageSection 7.3.1
ChDVC_LEVELDigital Volume Control LevelSection 7.3.2
10hDVC_SLEW_RATEDigital Volume Control Slew RateSection 7.3.3
18hAUDIO_HPF_N0Set Audio DC Blocker filter coefficientsSection 7.3.4
1ChAUDIO_HPF_N1Set Audio DC Blocker filter coefficientsSection 7.3.5
20hAUDIO_HPF_D1Set Audio DC Blocker filter coefficientsSection 7.3.6
54hTONE_GEN_CNTRL_01Tone generator Frequency Control registerSection 7.3.7
58hTONE_GEN_CNTRL_02Tone generator Frequency Control registerSection 7.3.8
5ChTONE_GEN_CNTRL_03Tone generator Frequency Control registerSection 7.3.9
60hTONE_GEN_CNTRL_04Tone generator Frequency Control registerSection 7.3.10
64hTONE_GEN_CNTRL_05Tone generator Frequency Control registerSection 7.3.11
68hTONE_GEN_CNTRL_06Tone generator amplitude control registerSection 7.3.12
6ChCLASSH_TUNING_01ClassH Tuning CoefficientSection 7.3.13
70hCLASSH_TUNING_02ClassH Tuning CoefficientSection 7.3.14
74hCLASSH_TUNING_03ClassH Tuning CoefficientSection 7.3.15
78hCLASSH_TUNING_04ClassH Tuning CoefficientSection 7.3.16
7ChCLASSH_TUNING_05ClassH Tuning CoefficientSection 7.3.17

7.3.1 PAGE Register (Address = 0h) [Reset = 00h]

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The devices memory map is divided into pages and books. This register sets the page.

Table 7-50 PAGE Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W0h Sets the device page.
  • 0h = Page 0
  • 1h = Page 1
  • FFh = Page 255

7.3.2 DVC_LEVEL Register (Address = Ch) [Reset = 400000h]

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Digital Volume Control Level

Table 7-51 DVC_LEVEL Register Field Descriptions
BitFieldTypeResetDescription
23-0DVC_LEVEL[23:0]R/W400000h Addresses 0xC to 0xE are combined. Can be configured using the PPC3 Software.

7.3.3 DVC_SLEW_RATE Register (Address = 10h) [Reset = 034A51h]

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Digital Volume Control Slew Rate

Table 7-52 DVC_SLEW_RATE Register Field Descriptions
BitFieldTypeResetDescription
23-0DVC_SLEW_RATE[23:0]R/W34A51h Addresses 0x10 to 0x12 are combined. Can be configured using the PPC3 Software.

7.3.4 AUDIO_HPF_N0 Register (Address = 18h) [Reset = 7FFBB6h]

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Set Audio DC Blocker filter coefficients

Table 7-53 AUDIO_HPF_N0 Register Field Descriptions
BitFieldTypeResetDescription
23-0AUDIO_HPF_N0[23:0]R/W7FFBB6h Addresses 0x18 to 0x1A are combined. Can be configured using the PPC3 Software.

7.3.5 AUDIO_HPF_N1 Register (Address = 1Ch) [Reset = 80044Ah]

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Set Audio DC Blocker filter coefficients

Table 7-54 AUDIO_HPF_N1 Register Field Descriptions
BitFieldTypeResetDescription
23-0AUDIO_HPF_N1[23:0]R/W80044Ah Addresses 0x1C to 0x1E are combined. Can be configured using the PPC3 Software.

7.3.6 AUDIO_HPF_D1 Register (Address = 20h) [Reset = 7FF76Ch]

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Set Audio DC Blocker filter coefficients

Table 7-55 AUDIO_HPF_D1 Register Field Descriptions
BitFieldTypeResetDescription
23-0AUDIO_HPF_D1[23:0]R/W7FF76Ch Addresses 0x20 to 0x22 are combined. Can be configured using the PPC3 Software.

7.3.7 TONE_GEN_CNTRL_01 Register (Address = 54h) [Reset = 7FFFEDh]

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Tone generator Frequency Control register

Table 7-56 TONE_GEN_CNTRL_01 Register Field Descriptions
BitFieldTypeResetDescription
23-0TONE_GEN_CNTRL_01[23:0]R/W7FFFEDh Addresses 0x54 to 0x56 are combined. Can be configured using the PPC3 Software.

7.3.8 TONE_GEN_CNTRL_02 Register (Address = 58h) [Reset = 4D0582h]

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Tone generator Frequency Control register

Table 7-57 TONE_GEN_CNTRL_02 Register Field Descriptions
BitFieldTypeResetDescription
23-0TONE_GEN_CNTRL_02[23:0]R/W4D0582h Addresses 0x58 to 0x5A are combined. Can be configured using the PPC3 Software.

7.3.9 TONE_GEN_CNTRL_03 Register (Address = 5Ch) [Reset = 002250h]

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Tone generator Frequency Control register

Table 7-58 TONE_GEN_CNTRL_03 Register Field Descriptions
BitFieldTypeResetDescription
23-0TONE_GEN_CNTRL_03[23:0]R/W2250h Addresses 0x5C to 0x5E are combined. Can be configured using the PPC3 Software.

7.3.10 TONE_GEN_CNTRL_04 Register (Address = 60h) [Reset = 42FC96h]

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Tone generator Frequency Control register

Table 7-59 TONE_GEN_CNTRL_04 Register Field Descriptions
BitFieldTypeResetDescription
23-0TONE_GEN_CNTRL_04[23:0]R/W42FC96h Addresses 0x60 to 0x62 are combined. Can be configured using the PPC3 Software.

7.3.11 TONE_GEN_CNTRL_05 Register (Address = 64h) [Reset = 000BB8h]

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Tone generator Frequency Control register

Table 7-60 TONE_GEN_CNTRL_05 Register Field Descriptions
BitFieldTypeResetDescription
23-0TONE_GEN_CNTRL_05[23:0]R/WBB8h Addresses 0x64 to 0x66 are combined. Can be configured using the PPC3 Software.

7.3.12 TONE_GEN_CNTRL_06 Register (Address = 68h) [Reset = 01235Ah]

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Tone generator amplitude control register

Table 7-61 TONE_GEN_CNTRL_06 Register Field Descriptions
BitFieldTypeResetDescription
23-0TONE_GEN_CNTRL_06[23:0]R/W1235Ah Addresses 0x68 to 0x6A are combined. Can be configured using the PPC3 Software.

7.3.13 CLASSH_TUNING_01 Register (Address = 6Ch) [Reset = 000280h]

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ClassH Tuning Coefficient

Table 7-62 CLASSH_TUNING_01 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_01[23:0]R/W280h Addresses 0x6C to 0x6E are combined. Can be configured using the PPC3 Software.

7.3.14 CLASSH_TUNING_02 Register (Address = 70h) [Reset = 800000h]

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ClassH Tuning Coefficient

Table 7-63 CLASSH_TUNING_02 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_02[23:0]R/W800000h Addresses 0x70 to 0x72 are combined. Can be configured using the PPC3 Software.

7.3.15 CLASSH_TUNING_03 Register (Address = 74h) [Reset = 507480h]

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ClassH Tuning Coefficient

Table 7-64 CLASSH_TUNING_03 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_03[23:0]R/W507480h Addresses 0x74 to 0x76 are combined. Can be configured using the PPC3 Software.

7.3.16 CLASSH_TUNING_04 Register (Address = 78h) [Reset = 400000h]

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ClassH Tuning Coefficient

Table 7-65 CLASSH_TUNING_04 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_04[23:0]R/W400000h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.

7.3.17 CLASSH_TUNING_05 Register (Address = 7Ch) [Reset = 006666h]

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ClassH Tuning Coefficient

Table 7-66 CLASSH_TUNING_05 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_05[23:0]R/W6666h Addresses 0x7C to 0x7E are combined. Can be configured using the PPC3 Software.