SLASFC5A September   2024  – October 2025 TAS2320

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 External Class-H Boost Controller
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.8 Typical Characteristics

TA = 25°C, VBAT = 3.6V, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ = 1, Noise gate disabled, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).

TAS2320 THD+N vs Output Power

RL = 8Ω

Figure 5-3 THD+N vs Output Power
TAS2320 THD+N vs Output Power

RL = 8Ω HW Pin Control

Figure 5-5 THD+N vs Output Power
TAS2320 THD+N vs Frequency

RL = 8Ω

Figure 5-7 THD+N vs Frequency
TAS2320 Efficiency vs Output Power

RL = 8Ω

Figure 5-9 Efficiency vs Output Power
TAS2320 Efficiency vs Output Power

RL = 8Ω HW Pin Control

Figure 5-11 Efficiency vs Output Power
TAS2320 Output Power vs PVDD Voltage

RL = 8 Ω

Figure 5-13 Output Power vs PVDD Voltage
TAS2320 Idle channel noise vs PVDD voltage

RL = 8 Ω

Figure 5-15 Idle channel noise vs PVDD voltage
TAS2320 PSRR vs Frequency

RL = 8 Ω

Figure 5-17 PSRR vs Frequency
TAS2320 Idle channel current vs VBAT voltage

RL = 8 Ω

Figure 5-19 Idle channel current vs VBAT voltage
TAS2320 THD+N vs Output Power

RL = 4Ω

Figure 5-4 THD+N vs Output Power
TAS2320 THD+N vs Output Power

RL = 4Ω HW Pin Control

Figure 5-6 THD+N vs Output Power
TAS2320 THD+N vs Frequency

RL = 4Ω

Figure 5-8 THD+N vs Frequency
TAS2320 Efficiency vs Output Power

RL = 4Ω

Figure 5-10 Efficiency vs Output Power
TAS2320 Efficiency vs Output Power

RL = 4Ω HW Pin Control

Figure 5-12 Efficiency vs Output Power
TAS2320 Output Power vs PVDD Voltage

RL = 4 Ω

Figure 5-14 Output Power vs PVDD Voltage
TAS2320 Audio channel frequency response

RL = 8 Ω

Figure 5-16 Audio channel frequency response
TAS2320 Idle channel current vs VDD voltage

RL = 8 Ω

Figure 5-18 Idle channel current vs VDD voltage
TAS2320 Idle channel current vs PVDD voltage

RL = 8 Ω

Figure 5-20 Idle channel current vs PVDD voltage