SLASFC5A September   2024  – October 2025 TAS2320

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 External Class-H Boost Controller
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6 PAGE 6 Registers

Table 7-91 lists the memory-mapped registers for the PAGE 6 registers. All register offset addresses not listed in Table 7-91 should be considered as reserved locations and the register contents should not be modified.

Table 7-91 PAGE 6 Registers
AddressAcronymDescriptionSection
0hPAGEDevice PageSection 7.6.1
1ChCLASSH_TUNING_07ClassH Tuning CoefficientSection 7.6.2
20hCLASSH_TUNING_08ClassH Tuning CoefficientSection 7.6.3
24hCLASSH_TUNING_09ClassH Tuning CoefficientSection 7.6.4
30hDEV_PERF_TUNING_14Device performance tuningSection 7.6.5
34hDEV_PERF_TUNING_24Device performance tuningSection 7.6.6
38hDEV_PERF_TUNING_18Device performance tuningSection 7.6.7
48hDEV_PERF_TUNING_25Device performance tuningSection 7.6.8
60hCLASSH_TUNING_10ClassH Tuning CoefficientSection 7.6.9
70hCLASSH_TUNING_11ClassH Tuning CoefficientSection 7.6.10
74hCLASSH_TUNING_12ClassH Tuning CoefficientSection 7.6.11
78hCLASSH_TUNING_13ClassH Tuning CoefficientSection 7.6.12
7ChCLASSH_TUNING_14ClassH Tuning CoefficientSection 7.6.13

7.6.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table.

The devices memory map is divided into pages and books. This register sets the page.

Table 7-92 PAGE Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W0h Sets the device page.
  • 0h = Page 0
  • 1h = Page 1
  • FFh = Page 255

7.6.2 CLASSH_TUNING_07 Register (Address = 1Ch) [Reset = 0A72ABh]

Return to the Summary Table.

ClassH Tuning Coefficient

Table 7-93 CLASSH_TUNING_07 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_07[23:0]R/WA72ABh Addresses 0x1C to 0x1E are combined. Can be configured using the PPC3 Software.

7.6.3 CLASSH_TUNING_08 Register (Address = 20h) [Reset = 103F46h]

Return to the Summary Table.

ClassH Tuning Coefficient

Table 7-94 CLASSH_TUNING_08 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_08[23:0]R/W103F46h Addresses 0x20 to 0x22 are combined. Can be configured using the PPC3 Software.

7.6.4 CLASSH_TUNING_09 Register (Address = 24h) [Reset = 0A45F1h]

Return to the Summary Table.

ClassH Tuning Coefficient

Table 7-95 CLASSH_TUNING_09 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_09[23:0]R/WA45F1h Addresses 0x24 to 0x26 are combined. Can be configured using the PPC3 Software.

7.6.5 DEV_PERF_TUNING_14 Register (Address = 30h) [Reset = 400000h]

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Device performance tuning

Table 7-96 DEV_PERF_TUNING_14 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_14[23:0]R/W400000h Addresses 0x30 to 0x32 are combined. Can be configured using the PPC3 Software.

7.6.6 DEV_PERF_TUNING_24 Register (Address = 34h) [Reset = 400000h]

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Device performance tuning

Table 7-97 DEV_PERF_TUNING_24 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_24[23:0]R/W400000h Addresses 0x34 to 0x36 are combined. Can be configured using the PPC3 Software.

7.6.7 DEV_PERF_TUNING_18 Register (Address = 38h) [Reset = 400000h]

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Device performance tuning

Table 7-98 DEV_PERF_TUNING_18 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_18[23:0]R/W400000h Addresses 0x38 to 0x3A are combined. Can be configured using the PPC3 Software.

7.6.8 DEV_PERF_TUNING_25 Register (Address = 48h) [Reset = 166666h]

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Device performance tuning

Table 7-99 DEV_PERF_TUNING_25 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_25[23:0]R/W166666h Addresses 0x48 to 0x4A are combined. Can be configured using the PPC3 Software.

7.6.9 CLASSH_TUNING_10 Register (Address = 60h) [Reset = 074969h]

Return to the Summary Table.

ClassH Tuning Coefficient

Table 7-100 CLASSH_TUNING_10 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_10[23:0]R/W74969h Addresses 0x60 to 0x62 are combined. Can be configured using the PPC3 Software.

7.6.10 CLASSH_TUNING_11 Register (Address = 70h) [Reset = 133333h]

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ClassH Tuning Coefficient

Table 7-101 CLASSH_TUNING_11 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_11[23:0]R/W133333h Addresses 0x70 to 0x72 are combined. Can be configured using the PPC3 Software.

7.6.11 CLASSH_TUNING_12 Register (Address = 74h) [Reset = 04999Ah]

Return to the Summary Table.

ClassH Tuning Coefficient

Table 7-102 CLASSH_TUNING_12 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_12[23:0]R/W4999Ah Addresses 0x74 to 0x76 are combined. Can be configured using the PPC3 Software.

7.6.12 CLASSH_TUNING_13 Register (Address = 78h) [Reset = 046666h]

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ClassH Tuning Coefficient

Table 7-103 CLASSH_TUNING_13 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_13[23:0]R/W46666h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.

7.6.13 CLASSH_TUNING_14 Register (Address = 7Ch) [Reset = 280000h]

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ClassH Tuning Coefficient

Table 7-104 CLASSH_TUNING_14 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_14[23:0]R/W280000h Addresses 0x7C to 0x7E are combined. Can be configured using the PPC3 Software.