SLASFC5A September   2024  – October 2025 TAS2320

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 External Class-H Boost Controller
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TAS2320 QFN Package Bottom View
Figure 4-1 QFN Package Bottom View
Pin Functions
PIN Type(1) DESCRIPTION
NAME NO.
DREG 26 P Digital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to an external load.
FSYNC 8 I I2S word clock or TDM frame sync.
GREG 17 P High-side gate CP regulator output. Do not connect to an external load.
GND 12, 22, 23, 25 P Connect to PCB ground plane. Strong connection to ground plane required through multiple vias.
IOVDD 5 P 1.8V or 3.3V Digital IO supply. Decouple to GND with capacitor.
IRQZ 6 O Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pullup is not used.
NC 13 - No connect. Keep floating.
OUT_N 19 O Class-D negative output.
OUT_P 20 O Class-D positive output.
PGND 21 P Class-D Power stage ground. Connect to PCB GND plane strongly through multiple vias.
PVDD 18 P Class-D power stage supply. Decouple to GND with capacitor.
SBCLK 9 I I2S or TDM serial bit clock.
SDIN 10 I I2S or TDM serial data input.
SDOUT 11 I/O I2S or TDM serial data output.
SDZ 7 I Active low hardware shutdown.
SEL1_I2C 16 I

HW Mode: Select 1 Pin. Amplifier gain level selection with volume ramp enable and disable options.

I2C Mode: Short to GND for I2C mode selection.
SEL2_SCL 4 I

HW Mode: Select 2 Pin. I2S, TDM, Left justified selection.

I2C Mode: Clock Pin. Pull up to IOVDD with a resistor.
SEL3_SDA 3 I/O

HW Mode: Select 3 Pin. Data valid rising edge and falling edge selection.

I2C Mode: Data Pin. Pull up to IOVDD with a resistor.
SEL4_ADR 2 I

HW Mode: Select 4 Pin.Y-bridge threshold configuration setting.

I2C Mode: I2C address pin.
SEL5_CLH 1 I/O

HW Mode: Select5 Pin. Connect to IOVDD.

I2C Mode: Class-H control. Shared boost output or external boost PWM generation. Short to GND if shared boost or external boost feature is not used.
VBAT 15 P Battery power supply input. Connect to a 2.5 to 5.5V supply and decouple with a capacitor.
14 I Battery power supply input. Connect to a 2.5 to 5.5V supply.
VDD 24 P Connect to 1.8V supply and decouple to GND with capacitor.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.