SLASFC5A September   2024  – October 2025 TAS2320

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 External Class-H Boost Controller
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4 PAGE 4 Registers

Table 7-67 lists the memory-mapped registers for the PAGE 4 registers. All register offset addresses not listed in Table 7-67 should be considered as reserved locations and the register contents should not be modified.

Table 7-67 PAGE 4 Registers
AddressAcronymDescriptionSection
0hPAGEDevice PageSection 7.4.1
8hVDD_MODE_THR_LVLVDD Y Bridge Set ThresholdSection 7.4.2
ChVDD_MODE_HYSTVDD Y Bridge Set Threshold hysterisisSection 7.4.3
18hMUSIC_EFF_MODE_THRSet Music Efficiency Mode ThresholdSection 7.4.4
1ChMUSIC_EFF_MODE_TIMERSet Music Efficiency Mode HysteresisSection 7.4.5
38hLIM_MAX_ATTLimiter Set Maximum AttenuationSection 7.4.6
3ChLIM_TH_MAXLimiter Set maximum audio limiting thresholdSection 7.4.7
40hLIM_TH_MINLimiter Set minimum audio limiting thresholdSection 7.4.8
44hLIM_INF_PTLimiter Set Inflection PointSection 7.4.9
48hLIM_SLOPELimiter Set SlopeSection 7.4.10
4ChLIM_ATK_RATELimiter Set Attack RateSection 7.4.11
50hLIM_RLS_RATELimiter Set Release RateSection 7.4.12
54hLIM_HLD_COUNTLimiter Set Hold CountSection 7.4.13
58hBOP_ATK_RATEBrown Out Protection Set Attack RateSection 7.4.14
5ChBOP_HLD_COUNTBrown Out Protection Set Hold CountSection 7.4.15
60hBOP_THR_LVLBrown Out Protection Set Threshold LevelSection 7.4.16
64hBOSD_THR_LVLBrown Out Protection ShutDown Set Threshold LevelSection 7.4.17
74hDEV_PERF_TUNING_01Device performance tuning registerSection 7.4.18
78hDEV_PERF_TUNING_02Device performance tuning registerSection 7.4.19

7.4.1 PAGE Register (Address = 0h) [Reset = 00h]

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The devices memory map is divided into pages and books. This register sets the page.

Table 7-68 PAGE Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W0h Sets the device page.
  • 0h = Page 0
  • 1h = Page 1
  • FFh = Page 255

7.4.2 VDD_MODE_THR_LVL Register (Address = 8h) [Reset = 50A3D7h]

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VDD Y Bridge Set Threshold

Table 7-69 VDD_MODE_THR_LVL Register Field Descriptions
BitFieldTypeResetDescription
23-0VDD_MODE_THR_LVL[23:0]R/W50A3D7h Addresses 0x8 to 0xA are combined. Can be configured using the PPC3 Software.

7.4.3 VDD_MODE_HYST Register (Address = Ch) [Reset = 00DA74h]

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VDD Y Bridge Set Threshold hysterisis

Table 7-70 VDD_MODE_HYST Register Field Descriptions
BitFieldTypeResetDescription
23-0VDD_MODE_HYST[23:0]R/WDA74h Addresses 0xC to 0xE are combined. Can be configured using the PPC3 Software.

7.4.4 MUSIC_EFF_MODE_THR Register (Address = 18h) [Reset = 0443F5h]

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Set Music Efficiency Mode Threshold

Table 7-71 MUSIC_EFF_MODE_THR Register Field Descriptions
BitFieldTypeResetDescription
23-0MUSIC_EFF_MODE_THR[23:0]R/W443F5h Addresses 0x18 to 0x1A are combined. Can be configured using the PPC3 Software.

7.4.5 MUSIC_EFF_MODE_TIMER Register (Address = 1Ch) [Reset = 000034h]

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Set Music Efficiency Mode Hysteresis

Table 7-72 MUSIC_EFF_MODE_TIMER Register Field Descriptions
BitFieldTypeResetDescription
23-0MUSIC_EFF_MODE_TIMER[23:0]R/W34h Addresses 0x1C to 0x1E are combined. Can be configured using the PPC3 Software.

7.4.6 LIM_MAX_ATT Register (Address = 38h) [Reset = 2D6A86h]

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Limiter Set Maximum Attenuation

Table 7-73 LIM_MAX_ATT Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_MAX_ATT[23:0]R/W2D6A86h Addresses 0x38 to 0x3A are combined. Can be configured using the PPC3 Software.

7.4.7 LIM_TH_MAX Register (Address = 3Ch) [Reset = 400000h]

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Limiter Set maximum audio limiting threshold

Table 7-74 LIM_TH_MAX Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_TH_MAX[23:0]R/W400000h Addresses 0x3C to 0x3E are combined. Can be configured using the PPC3 Software.

7.4.8 LIM_TH_MIN Register (Address = 40h) [Reset = 0A0000h]

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Limiter Set minimum audio limiting threshold

Table 7-75 LIM_TH_MIN Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_TH_MIN[23:0]R/WA0000h Addresses 0x40 to 0x42 are combined. Can be configured using the PPC3 Software.

7.4.9 LIM_INF_PT Register (Address = 44h) [Reset = 0D3333h]

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Limiter Set Inflection Point

Table 7-76 LIM_INF_PT Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_INF_PT[23:0]R/WD3333h Addresses 0x44 to 0x46 are combined. Can be configured using the PPC3 Software.

7.4.10 LIM_SLOPE Register (Address = 48h) [Reset = 100000h]

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Limiter Set Slope

Table 7-77 LIM_SLOPE Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_SLOPE[23:0]R/W100000h Addresses 0x48 to 0x4A are combined. Can be configured using the PPC3 Software.

7.4.11 LIM_ATK_RATE Register (Address = 4Ch) [Reset = 7C5E4Eh]

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Limiter Set Attack Rate

Table 7-78 LIM_ATK_RATE Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_ATK_RATE[23:0]R/W7C5E4Eh Addresses 0x4C to 0x4E are combined. Can be configured using the PPC3 Software.

7.4.12 LIM_RLS_RATE Register (Address = 50h) [Reset = 400179h]

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Limiter Set Release Rate

Table 7-79 LIM_RLS_RATE Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_RLS_RATE[23:0]R/W400179h Addresses 0x50 to 0x52 are combined. Can be configured using the PPC3 Software.

7.4.13 LIM_HLD_COUNT Register (Address = 54h) [Reset = 005DC0h]

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Limiter Set Hold Count

Table 7-80 LIM_HLD_COUNT Register Field Descriptions
BitFieldTypeResetDescription
23-0LIM_HLD_COUNT[23:0]R/W5DC0h Addresses 0x5C to 0x5E are combined. Can be configured using the PPC3 Software.

7.4.14 BOP_ATK_RATE Register (Address = 58h) [Reset = 78D67Ch]

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Brown Out Protection Set Attack Rate

Table 7-81 BOP_ATK_RATE Register Field Descriptions
BitFieldTypeResetDescription
23-0BOP_ATK_RATE[23:0]R/W78D67Ch Addresses 0x58 to 0x5A are combined. Can be configured using the PPC3 Software.

7.4.15 BOP_HLD_COUNT Register (Address = 5Ch) [Reset = 005DC0h]

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Brown Out Protection Set Hold Count

Table 7-82 BOP_HLD_COUNT Register Field Descriptions
BitFieldTypeResetDescription
23-0BOP_HLD_COUNT[23:0]R/W5DC0h Addresses 0x5C to 0x5E are combined. Can be configured using the PPC3 Software.

7.4.16 BOP_THR_LVL Register (Address = 60h) [Reset = 0B9999h]

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Brown Out Protection Set Threshold Level

Table 7-83 BOP_THR_LVL Register Field Descriptions
BitFieldTypeResetDescription
23-0BOP_THR_LVL[23:0]R/WB9999h Addresses 0x60 to 0x62 are combined. Can be configured using the PPC3 Software.

7.4.17 BOSD_THR_LVL Register (Address = 64h) [Reset = 0ACCCCh]

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Brown Out Protection ShutDown Set Threshold Level

Table 7-84 BOSD_THR_LVL Register Field Descriptions
BitFieldTypeResetDescription
23-0BOSD_THR_LVL[23:0]R/WACCCCh Addresses 0x64 to 0x66 are combined. Can be configured using the PPC3 Software.

7.4.18 DEV_PERF_TUNING_01 Register (Address = 74h) [Reset = 079BCCh]

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Device performance tuning register

Table 7-85 DEV_PERF_TUNING_01 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_01[23:0]R/W79BCCh Addresses 0x74 to 0x76 are combined. Can be configured using the PPC3 Software.

7.4.19 DEV_PERF_TUNING_02 Register (Address = 78h) [Reset = 000034h]

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Device performance tuning register

Table 7-86 DEV_PERF_TUNING_02 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_02[23:0]R/W34h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.