SLLSFM2A November   2024  – October 2025 TCAN2855-Q1 , TCAN2857-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VCC1 Regulator
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  nRST Pin
      5. 8.3.5  VEXCC Regulator
      6. 8.3.6  CAN FD Transceiver
        1. 8.3.6.1 Driver and Receiver Function
        2. 8.3.6.2 CAN Bus Biasing
      7. 8.3.7  LIN Transceiver
        1. 8.3.7.1 LIN Transmitter Characteristics
        2. 8.3.7.2 LIN Receiver Characteristics
        3. 8.3.7.3 LIN Termination
      8. 8.3.8  GND
      9. 8.3.9  LIMP Pin
      10. 8.3.10 High-side Switches (HSS1- HSS4)
      11. 8.3.11 WAKE1, WAKE2 and WAKE3/DIR Pins
        1. 8.3.11.1 WAKE Pins Alternate Configurations
          1. 8.3.11.1.1 VBAT monitoring
          2. 8.3.11.1.2 Direct Drive
      12. 8.3.12 SDO Pin
      13. 8.3.13 nCS Pin
      14. 8.3.14 SCK Pin
      15. 8.3.15 SDI Pin
      16. 8.3.16 Interrupt Function (nINT)
      17. 8.3.17 SW Pin
      18. 8.3.18 GFO Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
        3. 8.4.5.3 LIN Transceiver Faults ( TCAN2857-Q1)
      6. 8.4.6 Sleep Mode
      7. 8.4.7 Wake Functions
        1. 8.4.7.1 CAN Bus Wake Using CRXD Request (BWRR) in Sleep Mode
        2. 8.4.7.2 LIN Bus Wake
        3. 8.4.7.3 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.4.7.3.1 Static Wake
          2. 8.4.7.3.2 Cyclic Sensing Wake
        4. 8.4.7.4 Cyclic Wake
        5. 8.4.7.5 Direct Drive in Sleep Mode
        6. 8.4.7.6 Selective Wake-up
          1. 8.4.7.6.1 Selective Wake Mode
          2. 8.4.7.6.2 Frame Detection
          3. 8.4.7.6.3 Wake-Up Frame (WUF) Validation
          4. 8.4.7.6.4 WUF ID Validation
          5. 8.4.7.6.5 WUF DLC Validation
          6. 8.4.7.6.6 WUF Data Validation
          7. 8.4.7.6.7 Frame Error Counter
          8. 8.4.7.6.8 CAN FD Frame Tolerance
          9. 8.4.7.6.9 8Mbps Filtering
      8. 8.4.8 Protection Features
        1. 8.4.8.1  Fail-safe Features
          1. 8.4.8.1.1 Sleep Mode Using Sleep Wake Error
        2. 8.4.8.2  Device Reset
        3. 8.4.8.3  Floating Terminals
        4. 8.4.8.4  TXD Dominant Time Out (DTO)
        5. 8.4.8.5  LIN Bus Stuck Dominant System Fault: False Wake Up Lockout
        6. 8.4.8.6  CAN Bus Short Circuit Current Limiting
        7. 8.4.8.7  Thermal Shutdown
        8. 8.4.8.8  Under and Over Voltage Lockout and Unpowered Device
          1. 8.4.8.8.1 Under-voltage
            1. 8.4.8.8.1.1 VSUP and VHSS Under-voltage
            2. 8.4.8.8.1.2 VCC1 Under-voltage
            3. 8.4.8.8.1.3 VCC2 and VEXCC Under-voltage
            4. 8.4.8.8.1.4 VCAN Under-voltage
          2. 8.4.8.8.2 VCC1, VCC2 and VEXCC Over-voltage
          3. 8.4.8.8.3 VCC1, VCC2 and VEXCC Short Circuit
        9. 8.4.8.9  Watchdog
          1. 8.4.8.9.1 Watchdog Error Counter and Action
          2. 8.4.8.9.2 Watchdog SPI Programming
            1. 8.4.8.9.2.1 Watchdog Configuration Registers Lock and Unlock
          3. 8.4.8.9.3 Watchdog Timing
          4. 8.4.8.9.4 Question and Answer Watchdog
            1. 8.4.8.9.4.1 WD Question and Answer Basic Information
            2. 8.4.8.9.4.2 Question and Answer Register and Settings
            3. 8.4.8.9.4.3 WD Question and Answer Value Generation
              1. 8.4.8.9.4.3.1 Answer Comparison
              2. 8.4.8.9.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.4.8.9.4.4 Question and Answer WD Example
              1. 8.4.8.9.4.4.1 Example Configuration for Desired Behavior
              2. 8.4.8.9.4.4.2 Example of Performing a Question and Answer Sequence
        10. 8.4.8.10 Bus Fault Detection and Communication
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS):
        3. 8.5.1.3 SPI Clock Input (SCK):
        4. 8.5.1.4 SPI Data Input (SDI):
        5. 8.5.1.5 SPI Data Output (SDO):
      2. 8.5.2 EEPROM
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 9.1.2 CAN Termination
        1. 9.1.2.1 Termination
      3. 9.1.3 Channel Expansion
        1. 9.1.3.1 Channel Expansion for LIN
        2. 9.1.3.2 Channel Expansion for CAN FD
      4. 9.1.4 Device Brownout information
      5. 9.1.5 Typical Application
        1. 9.1.5.1 Design Requirements
          1. 9.1.5.1.1 LTXD Dominant State Timeout Application Note
        2. 9.1.5.2 Detailed Design Procedures
          1. 9.1.5.2.1 CAN Detailed Design Procedure
          2. 9.1.5.2.2 LIN Detailed Design Procedures
        3. 9.1.5.3 Application Curves
    2. 9.2 Power Supply Recommendations
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
  11. 10Registers
    1. 10.1 Registers
      1. 10.1.1  DEVICE_ID_y Register (Address = 00h + formula) [reset = xxh]
      2. 10.1.2  REV_ID Register (Address = 08h) [reset = 2Xh]
      3. 10.1.3  SPI_CONFIG Register (Address = 09h) [reset = 00h]
      4. 10.1.4  CRC_CNTL Register (Address = 0Ah) [reset = 00h]
      5. 10.1.5  CRC_POLY_SET (Address = 0Bh) [reset = 00h]
      6. 10.1.6  SBC_CONFIG (Address = 0Ch) [reset = 06h]
      7. 10.1.7  VREG_CONFIG1 (Address = 0Dh) [reset = 80h]
      8. 10.1.8  SBC_CONFIG1 Register (Address = 0Eh) [reset = 01h]
      9. 10.1.9  Scratch_Pad_SPI Register (Address = 0Fh) [reset = 00h]
      10. 10.1.10 CAN_CNTRL_1 Register (Address = 10h) [reset = 04h]
      11. 10.1.11 WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 00h]
      12. 10.1.12 WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 02h]
      13. 10.1.13 WD_CONFIG_1 Register (Address = 13h) [reset = 82h]
      14. 10.1.14 WD_CONFIG_2 Register (Address = 14h) [reset = 60h]
      15. 10.1.15 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      16. 10.1.16 WD_RST_PULSE Register (Address = 16h) [reset = 00h]
      17. 10.1.17 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      18. 10.1.18 FSM_CNTR Register (Address = 18h) [reset = 00h]
      19. 10.1.19 DEVICE_CONFIG0 Register (Address = 19h) [reset = 10h]
      20. 10.1.20 DEVICE_CONFIG1 (Address = 1Ah) [reset = 00h]
      21. 10.1.21 DEVICE_CONFIG2 (Address = 1Bh) [reset = 00h]
      22. 10.1.22 SWE_TIMER (Address = 1Ch) [reset = 28h]
      23. 10.1.23 LIN_CNTL (Address = 1Dh) [reset = 20h]
      24. 10.1.24 HSS_CNTL (Address = 1Eh) [reset = 00h]
      25. 10.1.25 PWM1_CNTL1 (Address = 1Fh) [reset = 00h]
      26. 10.1.26 PWM1_CNTL2 (Address = 20h) [reset = 00h]
      27. 10.1.27 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      28. 10.1.28 PWM2_CNTL1 (Address = 22h) [reset = 00h]
      29. 10.1.29 PWM2_CNTL2 (Address = 23h) [reset = 00h]
      30. 10.1.30 PWM2_CNTL3 (Address = 24h) [reset = 00h]
      31. 10.1.31 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      32. 10.1.32 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      33. 10.1.33 RSRT_CNTR (Address = 28h) [reset = 40h]
      34. 10.1.34 nRST_CNTL (Address = 29h) [reset = 2Ch]
      35. 10.1.35 WAKE_PIN_CONFIG3 Register (Address = 2Ah) [reset = E0h]
      36. 10.1.36 WAKE_PIN_CONFIG4 Register (Address = 2Bh) [reset = 22h]
      37. 10.1.37 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0Ah]
      38. 10.1.38 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      39. 10.1.39 WD_QA_QUESTION Register (Address = 2Fh) [reset = 3Ch]
      40. 10.1.40 SW_ID1 Register (Address = 30h) [reset = 00h]
      41. 10.1.41 SW_ID2 Register (Address = 31h) [reset = 00h]
      42. 10.1.42 SW_ID3 Register (Address = 32h) [reset = 00h]
      43. 10.1.43 SW_ID4 Register (Address = 33h) [reset = 00h]
      44. 10.1.44 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      45. 10.1.45 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      46. 10.1.46 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      47. 10.1.47 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      48. 10.1.48 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      49. 10.1.49 DATA_y Register (Address = 39h + formula) [reset = 00h]
      50. 10.1.50 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      51. 10.1.51 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      52. 10.1.52 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      53. 10.1.53 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      54. 10.1.54 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      55. 10.1.55 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      56. 10.1.56 HSS_CNTL2 (Address = 4Dh) [reset = 00h]
      57. 10.1.57 EEPROM_CONFIG (Address = 4Eh) [reset = 00h]
      58. 10.1.58 HSS_CNTL3 (Address = 4Fh) [reset = 00h]
      59. 10.1.59 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      60. 10.1.60 INT_1 Register (Address = 51h) [reset = 00h]
      61. 10.1.61 INT_2 Register (Address = 52h) [reset = 40h]
      62. 10.1.62 INT_3 Register (Address 53h) [reset = 00h]
      63. 10.1.63 INT_CANBUS_1 Register (Address = 54h) [reset = 00h]
      64. 10.1.64 INT_7 (Address = 55h) [reset = 00h]
      65. 10.1.65 INT_EN_1 Register (Address = 56h) [reset = FFh]
      66. 10.1.66 INT_EN_2 Register (Address = 57h) [reset = 7Eh]
      67. 10.1.67 INT_EN_3 Register (Address = 58h) [reset = FEh]
      68. 10.1.68 INT_EN_CANBUS_1 Register (Address = 59h) [reset = BFh]
      69. 10.1.69 INT_4 Register (Address = 5Ah) [reset = 00h]
      70. 10.1.70 INT_6 Register (Address 5Ch) [reset = 00h]
      71. 10.1.71 INT_EN_4 Register (Address = 5Eh) [reset = DFh]
      72. 10.1.72 INT_EN_6 Register (Address = 60h) [reset = FFh]
      73. 10.1.73 INT_EN_7 Register (Address = 62) [reset = FFh]
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 LIN Transceiver Physical Layer Standards
      3. 11.1.3 EMC Requirements:
      4. 11.1.4 Conformance Test Requirements:
      5. 11.1.5 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

8.5.2 EEPROM

The TCAN285x-Q1 family uses EEPROM for two purposes. The first is for device trimming and is not accessible. This portion of EEPROM is monitored and loaded upon power and when exiting sleep mode, checking for a valid CRC. If the CRC is not valid, this process is performed a total of eight times. If still not valid, INT_3 register 8'h53[0] is set to 1b. This means the device has an issue that can impact the performance and functionality.

The second use of the EEPROM is to allow the user to store specific device configurations. The configuration bits saved are provided in each register. To save the configuration to SPI CRC must be enabled for the save function at a minimum. Saving the configuration to EEPROM is accomplished by writing a 1b to register 8'h4E[7] and default code Ah to 8'h4E[3:0] followed by the CRC byte.

When in one-byte mode, see Table 8-27 for the procedure if the processor does not support CRC. Register 8'h4E[3:0] reads back 0h. Once the configuration bits have been stored to EEPROM, a 0b is read back from 8'h4E[7]. If a power on reset takes place the configuration of the device is reloaded from EEPROM. Table 8-29 provides the list of registers and the bits saved to EEPROM if used.

When two-byte mode needs to be programmed into EEPROM for the first time, or if the device is already in two-byte mode and the device configuration needs be saved in EEPROM, follow the procedure outlined in Table 8-28.

Note: The EEPROM can be reprogrammed a maximum of 500 times.

Table 8-27 Process for non-CRC capable processors (one-byte mode)
StepDescriptionRegisterDataSecond Data Byte
1Configure deviceSee Table 8-29N/A
2Set CRC Polynomial
  • 0x2F AutoSar (00h)
  • 0X1D SAE J1185 (01h)
8'h0B[0]
  • 00h, OR
  • 01h
N/A
3Enable SPI CRC if not enable8'h0A01hN/A
4Save to EERPOM8'h4E8Ah
  • 36h (CRC POLY_8_SET = 00h)
  • 0Ch (CRC POLY_8_SET = 01h)
5Disable SPI CRC if not supported8'h0A00h
  • Eh (CRC POLY_8_SET = 00h)
  • 6Bh (CRC POLY_8_SET = 01h)

Table 8-28 Process for Non-CRC Capable Processors (Two-byte Mode)
StepDescriptionRegisterDataSecond Data Byte
1Configure the device into two-byte mode (skip this step if a;ready in two-byte mode)8h'0980hN/A
2Perform any other configurations that need to be saved into EEPROM (Use two-byte SPI writes)See Table 8-29
3Readback register 8h'09/0A to confirm two-byte mode. This step is critical for saving to EEPROM.8h'0980h00h
4Save to EERPOM8'h4E8Ah36h

The saved configuration can be forced to check if the saved configuration CRC is valid but using register 8'h4E[6], EEPROM_CRC_CHK, = 1b. This takes approximately 200μs to complete. If CRC is valid then no action is taken, If CRC is not valid the device attempts this action eight times. If still not valid afterward the device sets an interrupt indicating there is an issue are INT_4 register 8'h5A[1], EEPROM_CRC_INT.

The following are power and reset scenarios and how the EEPROM is used.

  • UVSUP event; no action as registers are not lost
  • Power on reset event; EEPROM is read and registers restored in Init mode once VSUP > UVSUP33R
  • Soft reset; EEPROM is read and registers restored and device transitions to standby mode
  • Hard reset; EERPOM is read and registers restored and device transitions to Init mode
  • nRST input; EEPROM is read and register restored and device transitions to restart mode

Table 8-29 EEPROM Saved Registers and Bits
RegisterBits Saved
SPI_CONFIG Register (Address = 09h)0-3
SBC_CONFIG (Address = Ch)0-1, 6, 7
VREG_CONFIG1 (Address = Dh)0-7
SBC_CONFIG1 Register (Address = Eh) 0, 3-5, 7
WAKE_PIN_CONFIG1 Register (Address = 11h)0-4
WAKE_PIN_CONFIG2 Register (Address = 12h)0-1, 5 , 6
WD_CONFIG_1 Register (Address = 13h)0-7
WD_CONFIG_2 Register (Address = 14h)0, 5-7
WD_RST_PULSE Register (Address = 16h)4-7
DEVICE_CONFIG1 (Address = 1Ah)0, 4, 7
DEVICE_CONFIG2 (Address = 1Bh)0
SWE_TIMER (Address = 1Ch)3-7
nRST_CNTL (Address = 29h)5
WAKE_PIN_CONFIG4 Register (Address = 2Bh)0-1, 3, 4-5, 7
WD_QA_CONFIG Register (Address = 2Dh)0-7
HSS_CNTL3 Register (Address = 4Fh)0, 4