The TCAN285x-Q1 supports low power sleep and standby modes and uses a wake up from the CAN bus mechanism called bus wake using CRXD Request (BWRR). Once this pattern is received, the TCAN285x-Q1 automatically switches to standby mode from sleep mode and insert an interrupt onto the nINT pin, if enabled, to indicate to a host microprocessor that the bus is active, and the processor wakes up and services the TCAN285x-Q1. The low power receiver and bus monitor are enabled in sleep mode to allow for CRXD Wake Requests using the CAN bus. A wake-up request is output to the CRXD (driven low) as shown in Figure 8-29. The external CAN FD controller monitors CRXD for transitions (high to low) and reactivate the device to normal mode based on the CRXD Wake Request. The CAN bus terminals are weakly pulled to GND during this mode, see Figure 7-2.

This device uses the wake-up pattern (WUP) from ISO 11898-2: 2024 to qualify bus traffic into a request to wake the host microprocessor. The bus wake request is signaled to the integrated CAN FD controller by a falling edge and low corresponding to a “filtered” bus dominant on the CRXD terminal (BWRR).

The wake-up pattern (WUP) consists of

• A filtered dominant bus of at least t_{WK_FILTER} followed by
• A filtered recessive bus time of at least t_{WK_FILTER} followed by
• A second filtered dominant bus time of at least t_{WK_FILTER}
• A second filtered recessive bus time of at least t_{WK_FILTER}

Once the WUP is detected, the device starts issuing wake up requests (BWRR) on the CRXD pin. The behavior of this pin is determined by register 8'h12[2]. If 8'h12[2] = 0b the CRXD pin is pulled low once the WUP pattern has been received that meets the dominant, recessive, dominant filtered times. The first filtered dominant initiates the WUP and the bus monitor is now waiting on a filtered recessive, other bus traffic does not reset the bus monitor. Once a filtered recessive is received, the bus monitor is now waiting on a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon receiving of the second filtered dominant the bus monitor recognizes the WUP and transition to BWRR output. Immediately upon verification receiving a WUP the device transitions the bus monitor into BWRR mode. This is indicated on the CRXD pin by latching the pin low; thus, the CRXD output during BWRR matches the classical 8 pin CAN devices that used the single filtered dominant on the bus as the wake-up request mechanism from ISO 11898-2: 2024.

For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than t_{WK_FILTER} time. Due to variability in the t_{WK_FILTER} the following scenarios are applicable.

• Bus state times less than t_{WK_FILTER(MIN)} are never detected as part of a WUP; thus, no BWRR is generated.
• Bus state times between t_{WK_FILTER(MIN)} and t_{WK_FILTER(MAX)} can be detected as part of a WUP and a BWRR can be generated.
• Bus state times more than t_{WK_FILTER(MAX)} is always detected as part of a WUP; thus, a BWRR is always generated.

See Figure 8-29 for the timing diagram of the WUP.

The pattern and t_{WK_FILTER} time used for the WUP and BWRR prevents noise and bus stuck dominant faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a BWRR. If the device is switched to normal mode or an under-voltage event occurs on V_CC, the BWRR is lost. The WUP pattern must take place within the t_{WK_TIMEOUT} time; otherwise, the device is in a state waiting for the next recessive and then a valid WUP pattern.

If 8'h12[2] = 1b, the CRXD pin toggles low too high too low for t_TOGGLE = 10µS until the device is put into normal mode or listen mode. BWRR is active in standby mode upon power up and once coming out of sleep mode or certain fail-safe mode conditions. If a SPI write puts the device into standby mode, the CRXD pin is high until a wake event takes place. The CRXD pin then behaves as if in sleep mode.

Figure 8-29 Wake Up Pattern (WUP) and Bus Wake Using CRXD Request (BWRR)

Figure 8-30 Example Timing Diagram With CTXD DTO