SLLSFS6B September   2024  – October 2025

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up Detection
      2. 7.3.2  Current Limit Configuration
        1. 7.3.2.1 Current Limit Configuration in Pin-Mode
        2. 7.3.2.2 Current Limit Configuration in SPI mode
      3. 7.3.3  CQ Current Fault Detection, Indication and Auto Recovery
      4. 7.3.4  DO Current Fault Detection, Indication and Auto Recovery
      5. 7.3.5  CQ and DI Receivers
      6. 7.3.6  Fault Reporting
        1. 7.3.6.1 Thermal Warning, Thermal Shutdown
      7. 7.3.7  The Integrated Voltage Regulator (LDO)
      8. 7.3.8  Reverse Polarity Protection
      9. 7.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 7.3.10 Undervoltage Lock-Out (UVLO)
      11. 7.3.11 Interrupt Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 CQ and DO Tracking mode
    5. 7.5 SPI Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Driving Capacitive Loads
        2. 8.2.2.2 Driving Inductive Loads
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 TIOL221 Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

8.4.1 Layout Guidelines

  • Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals, layer 2 as power ground layer for LM, layer 3 for the 24V supply plane (LP), and layer 4 for the regulated output supply (VOUT).
  • Connect the thermal pad to LM with maximum amount of thermal vias for best thermal performance.
  • Use entire planes for LP, VOUT and LM for minimum inductance.
  • The LP terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The recommended minimum capacitor value is 100nF. The capacitor must have a voltage rating of 50V minimum (100V depending on maximum sensor supply fault rating) and an X5R or X7R dielectric.
  • The optimum placement of the capacitor is closest to the LP and LM terminals of the transceiver to reduce supply drops during large supply current loads. See Figure 8-8 for a PCB layout example.
  • Connect all open-drain control outputs via 10kΩ pull-up resistors to the VOUT plane to provide a defined voltage potential to the system controller inputs when the outputs are high-impedance.
  • If using pin mode, connect the RSET resistor between ILIM_ADJ1/2 and LM, as needed
  • Decouple the regulated output voltage at VOUT to ground with a low-ESR, ≥ 1μF, ceramic decoupling capacitor. The capacitor must have a voltage rating of 10V minimum and an X5R or X7R dielectric.