SLUSF25A September   2025  – November 2025 UCC27834 , UCC27884

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Undervoltage Lockout (UVLO)
      3. 6.3.3 Level Shifter
      4. 6.3.4 Output Stage
      5. 6.3.5 Low Propagation Delays and Tightly Matched Outputs
      6. 6.3.6 HS Node dV/dt
      7. 6.3.7 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC278X4 Power Losses
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Dynamic Electrical Characteristics

At VDD=VHB=15V, VSS=VHS=0, all voltages are with respect to VSS, no load on LO and HO, –40°C<TJ< +150°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
PROPAGATION DELAYS
tDLFF VLI falling to VLO falling CLOAD = 0pF, from VINL of LI to 90% of LO falling 29 45 ns
tDHFF VHI falling to VHO falling CLOAD = 0pF,  from VINL of HI to 90% of HO falling 29 45 ns
tDLRR VLI rising to VLO rising CLOAD = 0pF, from VINH of LI to 10% of LO rising 29 45 ns
tDHRR VHI rising to VHO rising CLOAD = 0pF, from VINH of HI to 10% of HO rising 29 45 ns
DELAY MATCHING
tMON HI OFF, LI ON TJ = 25°C, |tDHFF – tDLRR| 5 ns
tMON HI OFF, LI ON TJ = -40°C to 150°C, |tDHFF – tDLRR| 5 ns
tMOFF LI OFF, HI ON TJ = 25°C, |tDLFF – tDHRR| 5 ns
tMOFF LI OFF, HI ON TJ = -40°C to 150°C, |tDLFF – tDHRR| 5 ns
OUTPUT RISE AND FALL TIME
tR_LO LO rise time CLOAD = 1000pF, from 10% to 90% 7.5 ns
tR_HO HO rise time CLOAD = 1000pF, from 10% to 90% 7.5 ns
tF_LO LO fall time CLOAD = 1000pF, from 90% to 10% 6.5 ns
tF_HO HO fall time CLOAD = 1000pF, from 90% to 10% 6.5 ns
MISCELLANEOUS
tON Minimum HI/LI ON pulse that changes output state 0V to 5V input signal on HI & LI pins, CLOAD = 1nF 11 20 ns
tOFF Minimum HI/LI OFF pulse that changes output state 5V to 0V input signal on HI & LI pins, CLOAD = 1nF 11 20 ns