SLUSFM0 May   2025 TPS4816-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Bypass FET (G drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET's (GATE drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t Based Overcurrent Protection
          1. 8.3.3.1.1 I2t based Overcurrent Protection with Auto-Retry
          2. 8.3.3.1.2 I2t based Overcurrent Protection with Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage (UVLO) and Overvoltage (OV) Protection
      9. 8.3.9 TPS48161-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Capacitve Load
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.3 Active Mode (AM)

In this mode, charge pump, gate drivers and all protections are enabled. The main FET (GATE drive) can be tuned ON or OFF by driving INP high or low respectively and bypass FET (G drive) can be tuned ON or OFF by driving INP_G high or low respectively

The device exits active mode and enters shutdown mode when EN/UVLO is pulled low.

Protections available in active state are:

  • Input UVLO: Main FET (GATE drive) is turned OFF when voltage on EN/UVLO falls below V(UVLOF).

  • Input Overvoltage (OV) protection: GATE drives are turned OFF when voltage on OV pin voltage exceeds V(OVR) and FLT asserts low.

  • Charge pump UVLO: Main FET (GATE drive) is turned OFF when voltage between BST to SRC falls below V(BST_UVLOF) and FLT asserts low.

  • Main path I2t protection: Main FET (GATE drive) is turned OFF when voltage across CS1+ and CS1– remains above I2t start threshold (V(OCP)) for time set by the I2t factor based on CI2t. The device goes in auto-retry or latch-off based on the selected configuration and FLT asserts low.
  • Main path Short-circuit protection: Main FET (GATE drive) is turned OFF when voltage across CS1+ and CS1– exceeds the set short-circuit threshold (V(SCP)). The device goes in auto-retry or latch-off based on the selected configuration and FLT asserts low.