SLUSFM0 May   2025 TPS4816-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Bypass FET (G drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET's (GATE drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t Based Overcurrent Protection
          1. 8.3.3.1.1 I2t based Overcurrent Protection with Auto-Retry
          2. 8.3.3.1.2 I2t based Overcurrent Protection with Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage (UVLO) and Overvoltage (OV) Protection
      9. 8.3.9 TPS48161-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Capacitve Load
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.1 Charge Pump and Gate Driver output (VS, GATE, BST, SRC)

TPS4816-Q1 Gate Driver Figure 8-1 Gate Driver

Figure 8-1 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses a strong 0.5-A/2-A peak source/sink gate driver (GATE) for main FETs Q1, Q2 and 100-μA/0.39-A peak source/sink current gate driver (G) for bypass FET Q3. The strong gate drivers enable paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 12-V in active mode, 600-μA charge pump is derived from VS terminal and charges the external boot-strap capacitor, CBST that is placed across the gate driver (BST and SRC).

VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the CBST capacitor. After the voltage across CBST crosses V(BST_UVLOR), the GATE driver section is activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose CBST based on the external FET QG and allowed dip during FET turn ON. In active mode, the charge pump remains enabled until the BST to SRC voltage reaches VCP(HIGH_AM), typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to VCP(LOW_AM) typically at which point the charge pump is enabled.

The voltage between BST and SRC continue to charge and discharge between VCP(HIGH_AM) and VCP(LOW_AM) in active mode as shown in the below figure:

TPS4816-Q1 Charge Pump OperationFigure 8-2 Charge Pump Operation