SLUSFM0 May   2025 TPS4816-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Bypass FET (G drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET's (GATE drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t Based Overcurrent Protection
          1. 8.3.3.1.1 I2t based Overcurrent Protection with Auto-Retry
          2. 8.3.3.1.2 I2t based Overcurrent Protection with Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage (UVLO) and Overvoltage (OV) Protection
      9. 8.3.9 TPS48161-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Capacitve Load
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Switching Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 48 V, V(BST – SRC) = 12 V, V(SRC) = 0 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tGATE(INP_H) INP Turn ON propogation Delay INP ↑ to GATE  ↑,  CL(GATE) = 47 nF 1.2 2.5 µs
tGATE(INP_L) INP Turn OFF propogation Delay INP ↓ to GATE  ↓, CL(GATE) = 47 nF 0.35 1.5 µs
tG(INP_G_H) INP_G Turn ON propogation Delay INP_G ↑ to G  ↑, CL(G) = 1 nF 10 15 µs
tGATE(INP_G_L) INP_G Turn OFF propogation Delay INP_G ↓ to G  ↓, CL(G) = 1 nF 1 2.5 µs
tGATE(EN_OFF) EN Turn OFF Propogation Delay  EN ↓ to GATE ↓, CL(GATE) = 47 nF,
INP = High		 3.1 4.5 µs
tGATE(UVLO_OFF) UVLO Turn OFF Propogation Delay  UVLO ↓ to GATE  ↓, CL(GATE) = 47 nF,
INP = High		 4 6.5 µs
tGATE(OV_OFF) OV Turn OFF Propogation Delay  OV ↓ to GATE ↓, CL(GATE) = 47 nF 4 6.5 µs
tGATE(UVLO_ON) UVLO to GATE Turn ON Propogation Delay with CBT pre-biased > VPORF and INP kept high EN/UVLO ↑ to GATE ↑, CL(GATE) = 47 nF,
INP = High,		 8.5 25 µs
tGATE(VS_OFF) GATE Turn OFF Propogation Delay with VS falling < VPORF and INP, EN/UVLO kept high VS ↓ (cross VPORF) to GATE ↓,
CL(GATE) = 47 nF,
INP = EN/UVLO = 2V		 25 40 µs
tSC Short Circuit Protection propogation Delay in Active Mode V(CS1+–CS1-) ↑ V(SCP) to GATE  ↓,
CL(GATE) = 47 nF		 3.9 5 µs
tBYPASS_SC Short Circuit Protection propogation Delay in Bypass path (Powerup into short with INP_G = High) V(DRN–CS2-) ↑ V(BYPASS_SCP) to G ↓,
CL(G) = 1 nF,
V(INP_G) = 2 V		 3.1 4.5 µs
tGATE(FLT_ASSERT) FLT assertion delay during short circuit V(CS1+–CS1–)↑ V(SCP) to FLT  ↓ 15 21 µs
tGATE(FLT_DE_ASSERT) FLT de-assertion delay during short circuit V(CS1+–CS1–)↓ V(SCP) to FLT  ↑ 3.8 µs
tGATE(FLT_ASSERT_BSTUVLO) FLT assertion delay during GATE Drive UVLO V(GATE–SRC)  ↓ V(BSTUVLOR) to FLT ↓ 30 µs
tGATE(FLT_DE_ASSERT_BSTUVLO) FLT de-assertion delay during GATE Drive UVLO V(GATE–SRC)  ↑ V(BSTUVLOR) to FLT ↑ 15 µs
t(IDIR_DELAY) Delay for current direction indication on I_DIR pin V(SNS)  ↑ or ↓ to V(I_DIR) ↑ or ↓
 		 6.5 10 µs