SLUSFX8 September   2026 UCC218302-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Insulation Specifications
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supply
      2. 6.3.2  VCC Undervoltage Lockout (UVLO)
      3. 6.3.3  Input Filters for IN+, IN-, and RST/EN
      4. 6.3.4  Active Pulldown
      5. 6.3.5  Short Circuit Clamping
      6. 6.3.6  Internal Active Miller Clamp
      7. 6.3.7  Desaturation (DESAT) Protection
      8. 6.3.8  Soft Shutdown (SSD)
      9. 6.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 6.3.10 Output Gate Voltage Monitor
      11. 6.3.11 Active Short Circuit (ASC) Support
      12. 6.3.12 Overtemperature Protection
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Schematic
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Input Filters for IN+, IN-, and RST/EN
        2. 7.2.3.2 FLT, RDY, and RST/EN Pin Circuitry
        3. 7.2.3.3 Gate Driver Output Resistors
        4. 7.2.3.4 Overcurrent and Short Circuit Protection With DESAT
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

6.3.10 Output Gate Voltage Monitor

Output gate voltage monitoring is implemented to make sure the gate driver output matches the inputs, IN+ and IN-. When the PWM signal ('IN+' - 'IN-') is high, the output is compared to the VGMHI reference. When the PWM signal is low, the output is compared to the VGMLO reference. Real-time gate monitor feedback is provided on the low-voltage side OUT_FB pin. The output status given on the OUT_FB pin can be compared to the PWM input by the MCU to determine if the system is operating properly or if a fault condition exists. See Figure 6-12 for a block diagram, Figure 6-13 for a timing diagram, and Package Information for a truth table of the output gate voltage monitor feature.

UCC218302-Q1 Output Gate Voltage Monitor Figure 6-12 Output Gate Voltage Monitor
UCC218302-Q1 Output Gate Voltage Monitor Timing Diagram Figure 6-13 Output Gate Voltage Monitor Timing Diagram
Table 6-1 Output Gate Voltage Monitor Steady State Truth Table
PWM ('IN+' - 'IN-') GATE VOLTAGE OUT_FB
L VGATE < VGMLO L
L VGATE > VGMLO H
H VGATE < VGMHI L
H VGATE > VGMHI H