SLVAE09B July   2018  – August 2021 TPS560430

 

  1.   Trademarks
  2. 1Introduction
  3. 2Peak Current Mode Loop Modeling
    1. 2.1 Overall Control Block Diagram and Transfer Function Derivation
    2. 2.2 Inside Current Loop Model
    3. 2.3 Overall Loop Model
    4. 2.4 Inductor and Output Capacitor Design Limits
    5. 2.5 The Equation to Calculate Bandwidth and Phase Margin
  4. 3Inductor and Output Capacitor Design
    1. 3.1 Inductor Design
    2. 3.2 Output Capacitor Design
    3. 3.3 Simulation and Bench Verification
  5. 4Summary
  6. 5References
  7. 6Revision History

3.3 Simulation and Bench Verification

Figure 3-1 shows the schematic for bench verification. SIMPLIS is used to simulate the loop response as shown in Figure 3-2. Figure 3-3 and Figure 3-4 are the loop responses from the SIMPLIS simulation and bench test under VIN = 12 V, VO = 5 V, IO = 0.6 A, and fSW = 1.1 MHz. Table 3-2 compares the calculation results, simulation results, and bench measurement at different VIN. It can be seen that the proposed model in this application report is accurate.

GUID-E20EF77C-001C-4EC9-A947-1C06DC700F41-low.gifFigure 3-1 TPS560430XF Design With 5-V Output
GUID-E46DCB1C-9D38-44D7-A452-499765E34052-low.gifFigure 3-2 Schematic of A Simplified SIMPLIS Model
GUID-474C5A66-13F5-49F4-80F6-5A5331D53B48-low.gif Figure 3-3 Bode Plot Simulation Result at VIN = 12 V, IO = 0.6 A
GUID-87DC977D-C5E7-4D5F-B6A5-99C250D04A9C-low.gif Figure 3-4 Bode Plot Test Result at VIN = 12 V, IO = 0.6 A
Table 3-2 Calculation, Simulation, and Bench Measurement Results Comparison
VIN (V) IO (A) CALCULATION RESULTS SIMULATION RESULTS BENCH MEASUREMENT
fc (kHz) PHASE MARGIN (°) fc (kHz) PHASE MARGIN (°) fc (kHz) PHASE MARGIN (°)
7 0.1 23.4 59.2 22.8 61.3 23.6 58.4
7 0.6 23.4 62.2 22.7 64.4 24.7 61.7
12 0.1 23.4 61.2 22.9 62.8 24.6 60.3
12 0.6 23.4 64.2 22.8 65.9 25.1 64
36 0.1 23.4 63 22.9 64.3 23.7 61.1
36 0.6 23.4 66 22.9 67.4 23.9 66.3