SLVAE09B July   2018  – August 2021 TPS560430

 

  1.   Trademarks
  2. 1Introduction
  3. 2Peak Current Mode Loop Modeling
    1. 2.1 Overall Control Block Diagram and Transfer Function Derivation
    2. 2.2 Inside Current Loop Model
    3. 2.3 Overall Loop Model
    4. 2.4 Inductor and Output Capacitor Design Limits
    5. 2.5 The Equation to Calculate Bandwidth and Phase Margin
  4. 3Inductor and Output Capacitor Design
    1. 3.1 Inductor Design
    2. 3.2 Output Capacitor Design
    3. 3.3 Simulation and Bench Verification
  5. 4Summary
  6. 5References
  7. 6Revision History

4 Summary

For an internally compensated, peak current mode buck converter, consider the loop response when designing inductor and output capacitor. This application report simplifies the inside current loop as a single pole, provides the constraint to ensure loop stability, and gives out an equation to calculate bandwidth and phase margin. The inductor and output capacitor is designed step-by-step considering loop response. The theory is verified by simulation and bench measurement results.