Figure 2-3 shows the Bode plot with proper inductor and output capacitor design. f_c ≫ f_{P_OUT}, f_c ≫ f_{Z_EA}, f_c ≪ f_{P_EA}, f_c ≪ f_{P_ci}, f_c ≪ f_{Z_OUT}

Figure 2-3 Bode Plot Model for PCM Buck Converter

The gain curve must go across 0 dB with a -20 dB/dec slew rate, so that the phase margin is enough. The zero introduced by the compensation network f_{Z_EA} cancels the pole of output impedance f_{P_OUT}, and they are placed far before crossover frequency: f_{P_OUT} ≪ f_c, f_{Z_EA} ≪ f_c. The parasitic capacitor of error amplifier C_{O_EA} is quite small, so f_{P_EA} ≫ f_c.

If L is too large, the pole introduced by the current loop f_{P_ci} is smaller than the crossover frequency f_c. The gain curve goes across 0 dB with a -40 dB/dec slew rate, and the phase margin is not enough. Besides, the loop response is influenced by V_IN since f_{P_ci} is influenced by V_IN. To prevent that from happening, L must be properly designed to ensure f_{P_ci} ≫ f_c. Equation 12 calculates the maximum inductor value.

Equation 12.

If the Equivalent Series Resistance (ESR) of output capacitor is too large, the zero introduced by the output capacitor f_{Z_OUT} is smaller than the crossover frequency f_c. The gain curve has a 0 dB/dec slew rate after f_{Z_OUT}, which makes the crossover frequency too large. Some high frequency poles introduced by the parasitic parameters in the IC influence the phase margin, and the phase margin is not enough. To prevent that, ESR of the output capacitor must be properly designed to ensure f_{Z_OUT} ≫ f_c. Equation 13 calculates the maximum ESR.

Equation 13.