SLVSHK9 December   2024 TPS546B26

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
        1. 6.3.1.1 Loop Compensation
      2. 6.3.2  Internal VCC LDO and Using an External Bias on VCC Pin and VDRV Pin
      3. 6.3.3  Input Undervoltage Lockout (UVLO)
        1. 6.3.3.1 Fixed VCC_OK UVLO
        2. 6.3.3.2 Fixed VDRV UVLO
        3. 6.3.3.3 Programmable PVIN UVLO
        4. 6.3.3.4 Control (CNTL) Enable
      4. 6.3.4  Differential Remote Sense and Internal, External Feedback Divider
      5. 6.3.5  Set the Output Voltage and VORST#
      6. 6.3.6  Start-Up and Shutdown
      7. 6.3.7  Dynamic Voltage Slew Rate
      8. 6.3.8  Set Switching Frequency
      9. 6.3.9  Switching Node (SW)
      10. 6.3.10 Overcurrent Limit and Low-side Current Sense
      11. 6.3.11 Negative Overcurrent Limit
      12. 6.3.12 Zero-Crossing Detection
      13. 6.3.13 Input Overvoltage Protection
      14. 6.3.14 Output Overvoltage and Undervoltage Protection
      15. 6.3.15 Overtemperature Protection
      16. 6.3.16 Telemetry
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 DCM Light Load Operation
      3. 6.4.3 Powering the Device From a 12V Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
      5. 6.4.5 Pin-Strapping
        1. 6.4.5.1 Programming MSEL1
        2. 6.4.5.2 Programming PMB_ADDR
        3. 6.4.5.3 Programming MSEL2
        4. 6.4.5.4 Programming VSEL\FB
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus® Commands
  8. 7 Register Maps
    1. 7.1  Conventions for Documenting Block Commands
    2. 7.2  (01h) OPERATION
    3. 7.3  (02h) ON_OFF_CONFIG
    4. 7.4  (03h) CLEAR_FAULTS
    5. 7.5  (0Eh) PASSKEY
    6. 7.6  (10h) WRITE_PROTECT
    7. 7.7  (15h) STORE_USER_ALL
    8. 7.8  (16h) RESTORE_USER_ALL
    9. 7.9  (19h) CAPABILITY
    10. 7.10 (1Bh) SMBALERT_MASK
    11. 7.11 (20h) VOUT_MODE
    12. 7.12 (21h) VOUT_COMMAND
    13. 7.13 (22h) VOUT_TRIM
    14. 7.14 (24h) VOUT_MAX
    15. 7.15 (25h) VOUT_MARGIN_HIGH
    16. 7.16 (26h) VOUT_MARGIN_LOW
    17. 7.17 (27h) VOUT_TRANSITION_RATE
    18. 7.18 (29h) VOUT_SCALE_LOOP
    19. 7.19 (2Ah) VOUT_SCALE_MONITOR
    20. 7.20 (2Bh) VOUT_MIN
    21. 7.21 (33h) FREQUENCY_SWITCH
    22. 7.22 (35h) VIN_ON
    23. 7.23 (36h) VIN_OFF
    24. 7.24 (39h) IOUT_CAL_OFFSET
    25. 7.25 (40h) VOUT_OV_FAULT_LIMIT
    26. 7.26 (41h) VOUT_OV_FAULT_RESPONSE
    27. 7.27 (42h) VOUT_OV_WARN_LIMIT
    28. 7.28 (43h) VOUT_UV_WARN_LIMIT
    29. 7.29 (44h) VOUT_UV_FAULT_LIMIT
    30. 7.30 (45h) VOUT_UV_FAULT_RESPONSE
    31. 7.31 (46h) IOUT_OC_FAULT_LIMIT
    32. 7.32 (48h) IOUT_OC_LV_FAULT_LIMIT
    33. 7.33 (49h) IOUT_OC_LV_FAULT_RESPONSE
    34. 7.34 (4Ah) IOUT_OC_WARN_LIMIT
    35. 7.35 (4Fh) OT_FAULT_LIMIT
    36. 7.36 (50h) OT_FAULT_RESPONSE
    37. 7.37 (51h) OT_WARN_LIMIT
    38. 7.38 (55h) VIN_OV_FAULT_LIMIT
    39. 7.39 (60h) TON_DELAY
    40. 7.40 (61h) TON_RISE
    41. 7.41 (64h) TOFF_DELAY
    42. 7.42 (65h) TOFF_FALL
    43. 7.43 (78h) STATUS_BYTE
    44. 7.44 (79h) STATUS_WORD
    45. 7.45 (7Ah) STATUS_VOUT
    46. 7.46 (7Bh) STATUS_IOUT
    47. 7.47 (7Ch) STATUS_INPUT
    48. 7.48 (7Dh) STATUS_TEMPERATURE
    49. 7.49 (7Eh) STATUS_CML
    50. 7.50 (7Fh) STATUS_OTHER
    51. 7.51 (80h) STATUS_MFR_SPECIFIC
    52. 7.52 (88h) READ_VIN
    53. 7.53 (8Bh) READ_VOUT
    54. 7.54 (8Ch) READ_IOUT
    55. 7.55 (8Dh) READ_TEMPERATURE_1
    56. 7.56 (98h) PMBUS_REVISION
    57. 7.57 (99h) MFR_ID
    58. 7.58 (9Ah) MFR_MODEL
    59. 7.59 (9Bh) MFR_REVISION
    60. 7.60 (ADh) IC_DEVICE_ID
    61. 7.61 (AEh) IC_DEVICE_REV
    62. 7.62 (D1h) SYS_CFG_USER1
    63. 7.63 (D3h) PMBUS_ADDR
    64. 7.64 (D4h) COMP
    65. 7.65 (D5h) VBOOT_OFFSET_1
    66. 7.66 (D8h) PIN_DETECT_OVERRIDE
    67. 7.67 (D9h) NVM_CHECKSUM
    68. 7.68 (DAh) READ_TELEMETRY
    69. 7.69 (DBh) STATUS_ALL
    70. 7.70 (DDh) EXT_WRITE_PROTECTION
    71. 7.71 (DEh) IMON_CAL
    72. 7.72 (FCh) FUSION_ID0
    73. 7.73 (FDh) FUSION_ID1
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Inductor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 Compensation Selection
        5. 8.2.3.5 VCC and VRDV Bypass Capacitors
        6. 8.2.3.6 BOOT Capacitor Selection
        7. 8.2.3.7 VOSNS and GOSNS Capacitor Selection
        8. 8.2.3.8 PMBus Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on EVM
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.66 (D8h) PIN_DETECT_OVERRIDE

CMD Address D8h
Write Transaction: Write Word
Read Transaction: Read Word
Format: Unsigned Binary (2 bytes)
NVM Back-up: EEPROM
Updates: On-the-fly (Selection requires power-cycle)

This register contains bits for overriding selected functions that can be set through NVM or pin-strapping. Pin-programmed values override NVM values (DEFAULT or USER STORE). Setting a "1" in each bit of this register will allow DEFAULT or USER STORE values instead of the pin-programmed value associated with that bit.

In order for an override bit to affect a related command, the user has to write the bit, store to EEPROM, and power-cycle the part.

Return to Supported PMBus Commands.

Figure 7-74 Register Map
15 14 13 12 11 10 9 8
R/W R R/W R/W R/W R/W R/W R/W
OVRD_PD 0 0 0 OVRD_SS OVRD_FLT_R_ESP OVRD_PMB_ADDR 0
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
0 OVRD_MODE OVRD_FSW OVRD_RAMP OVRD_GAIN OVRD_OCL 0 OVRD_VSEL
LEGEND: R/W = Read/Write; R = Read only
Table 7-79 Register Field Descriptions
Bit Field Access Reset Description
15 OVRD_PD R/W NVM

0b: Pin detection is active according to the remaining bits in this command.

1b: Pin detection is overridden, regardless of other bits in this command
14:12 0 R 0b Not supported and always set to 0. Attempts to write to this bit will be ignored.
13:12 0 R/W 00b Not supported and always set to 0.
11 OVRD_SS R/W NVM Override soft-start pin-strap value.

0b: Pin-strap results determine the soft-start value.

1b: Pin-strap results for TON_RISE are ignored. The values from NVM remain in effect until values are written to the TON_RISE register.
10 OVRD_FLT_RESP R/W NVM Override fault response pin-strap value.

0b: Pin-strap results determine the fault response.

1b: Pin-strap results for FAULT_RESPONSE are ignored. The values from NVM remain in effect until values are written to the VOUT_OV_FAULT_RESPONSE, VOUT_UV_FAULT_RESPONSE, or OT_FAULT_RESPONSE registers.
9 OVRD_PMB_ADDR R/W NVM Override PMBus Address pin-strap value.

0b: Pin-strap results determine the PMBus Address value.

1b: Pin-strap results for PMBus_ADDR are ignored. The values from NVM remain in effect until values are written to the PMBus_ADDR register.
8:7 0 R/W 00b Not supported and always set to 0.
6 OVRD_MODE R/W NVM Override Mode pin-strap value.

0b: Pin-strap results determine the Mode value.

1b: Pin-strap results or FCCM/DCM light load operation are ignored. The values from NVM remain in effect until values are written to the SYS_CFG_USER1 register.
5 OVRD_FSW R/W NVM Override Frequency Switch pin-strap value.

0b: Pin-strap results determine the Frequency Switch value.

1b: Pin-strap results for FREQUENCY_SWITCH are ignored. The values from NVM remain in effect until values are written to the FREQUENCY_SWITCH register.
4 OVRD_RAMP R/W NVM Override RAMP pin-strap value.

0b: Pin-strap results determine the RAMP value.

1b: Pin-strap results for RAMP in COMP are ignored. The values from NVM remain in effect until values are written to the COMP register.
3 OVRD_GAIN R/W NVM Override GAIN pin-strap value.

0b: Pin-strap results determine the GAIN values.

1b: Pin-strap results for GAIN in COMP are ignored. The values from NVM remain in effect until values are written to the COMP register.
2 OVRD_OCL R/W NVM Override Overcurrent Limit (OCL) pin-strap value.

0b: Pin-strap results determine the OCL value.

1b: Pin-strap results IOUT_OC_FAULT_LIMIT are ignored. The values from NVM remain in effect until values are written to the IOUT_OC_FAULT_LIMIT register.
1 0 R/W NVM Not supported and always set to 0.
0 OVRD_VSEL R/W NVM Override VSEL pin-strap value.

0b: Pin-strap results determine the VSEL value. Ignored if external resistor divider is chosen.

1b: Pin-strap results for VSEL are ignored. The values from NVM remain in effect until values are written to the VBOOT_1, VOUT_SCALE_LOOP, VOUT_COMMAND, VOUT_MAX, or VOUT_MIN registers.