SLVSHK9 December   2024 TPS546B26

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
        1. 6.3.1.1 Loop Compensation
      2. 6.3.2  Internal VCC LDO and Using an External Bias on VCC Pin and VDRV Pin
      3. 6.3.3  Input Undervoltage Lockout (UVLO)
        1. 6.3.3.1 Fixed VCC_OK UVLO
        2. 6.3.3.2 Fixed VDRV UVLO
        3. 6.3.3.3 Programmable PVIN UVLO
        4. 6.3.3.4 Control (CNTL) Enable
      4. 6.3.4  Differential Remote Sense and Internal, External Feedback Divider
      5. 6.3.5  Set the Output Voltage and VORST#
      6. 6.3.6  Start-Up and Shutdown
      7. 6.3.7  Dynamic Voltage Slew Rate
      8. 6.3.8  Set Switching Frequency
      9. 6.3.9  Switching Node (SW)
      10. 6.3.10 Overcurrent Limit and Low-side Current Sense
      11. 6.3.11 Negative Overcurrent Limit
      12. 6.3.12 Zero-Crossing Detection
      13. 6.3.13 Input Overvoltage Protection
      14. 6.3.14 Output Overvoltage and Undervoltage Protection
      15. 6.3.15 Overtemperature Protection
      16. 6.3.16 Telemetry
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 DCM Light Load Operation
      3. 6.4.3 Powering the Device From a 12V Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
      5. 6.4.5 Pin-Strapping
        1. 6.4.5.1 Programming MSEL1
        2. 6.4.5.2 Programming PMB_ADDR
        3. 6.4.5.3 Programming MSEL2
        4. 6.4.5.4 Programming VSEL\FB
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus® Commands
  8. 7 Register Maps
    1. 7.1  Conventions for Documenting Block Commands
    2. 7.2  (01h) OPERATION
    3. 7.3  (02h) ON_OFF_CONFIG
    4. 7.4  (03h) CLEAR_FAULTS
    5. 7.5  (0Eh) PASSKEY
    6. 7.6  (10h) WRITE_PROTECT
    7. 7.7  (15h) STORE_USER_ALL
    8. 7.8  (16h) RESTORE_USER_ALL
    9. 7.9  (19h) CAPABILITY
    10. 7.10 (1Bh) SMBALERT_MASK
    11. 7.11 (20h) VOUT_MODE
    12. 7.12 (21h) VOUT_COMMAND
    13. 7.13 (22h) VOUT_TRIM
    14. 7.14 (24h) VOUT_MAX
    15. 7.15 (25h) VOUT_MARGIN_HIGH
    16. 7.16 (26h) VOUT_MARGIN_LOW
    17. 7.17 (27h) VOUT_TRANSITION_RATE
    18. 7.18 (29h) VOUT_SCALE_LOOP
    19. 7.19 (2Ah) VOUT_SCALE_MONITOR
    20. 7.20 (2Bh) VOUT_MIN
    21. 7.21 (33h) FREQUENCY_SWITCH
    22. 7.22 (35h) VIN_ON
    23. 7.23 (36h) VIN_OFF
    24. 7.24 (39h) IOUT_CAL_OFFSET
    25. 7.25 (40h) VOUT_OV_FAULT_LIMIT
    26. 7.26 (41h) VOUT_OV_FAULT_RESPONSE
    27. 7.27 (42h) VOUT_OV_WARN_LIMIT
    28. 7.28 (43h) VOUT_UV_WARN_LIMIT
    29. 7.29 (44h) VOUT_UV_FAULT_LIMIT
    30. 7.30 (45h) VOUT_UV_FAULT_RESPONSE
    31. 7.31 (46h) IOUT_OC_FAULT_LIMIT
    32. 7.32 (48h) IOUT_OC_LV_FAULT_LIMIT
    33. 7.33 (49h) IOUT_OC_LV_FAULT_RESPONSE
    34. 7.34 (4Ah) IOUT_OC_WARN_LIMIT
    35. 7.35 (4Fh) OT_FAULT_LIMIT
    36. 7.36 (50h) OT_FAULT_RESPONSE
    37. 7.37 (51h) OT_WARN_LIMIT
    38. 7.38 (55h) VIN_OV_FAULT_LIMIT
    39. 7.39 (60h) TON_DELAY
    40. 7.40 (61h) TON_RISE
    41. 7.41 (64h) TOFF_DELAY
    42. 7.42 (65h) TOFF_FALL
    43. 7.43 (78h) STATUS_BYTE
    44. 7.44 (79h) STATUS_WORD
    45. 7.45 (7Ah) STATUS_VOUT
    46. 7.46 (7Bh) STATUS_IOUT
    47. 7.47 (7Ch) STATUS_INPUT
    48. 7.48 (7Dh) STATUS_TEMPERATURE
    49. 7.49 (7Eh) STATUS_CML
    50. 7.50 (7Fh) STATUS_OTHER
    51. 7.51 (80h) STATUS_MFR_SPECIFIC
    52. 7.52 (88h) READ_VIN
    53. 7.53 (8Bh) READ_VOUT
    54. 7.54 (8Ch) READ_IOUT
    55. 7.55 (8Dh) READ_TEMPERATURE_1
    56. 7.56 (98h) PMBUS_REVISION
    57. 7.57 (99h) MFR_ID
    58. 7.58 (9Ah) MFR_MODEL
    59. 7.59 (9Bh) MFR_REVISION
    60. 7.60 (ADh) IC_DEVICE_ID
    61. 7.61 (AEh) IC_DEVICE_REV
    62. 7.62 (D1h) SYS_CFG_USER1
    63. 7.63 (D3h) PMBUS_ADDR
    64. 7.64 (D4h) COMP
    65. 7.65 (D5h) VBOOT_OFFSET_1
    66. 7.66 (D8h) PIN_DETECT_OVERRIDE
    67. 7.67 (D9h) NVM_CHECKSUM
    68. 7.68 (DAh) READ_TELEMETRY
    69. 7.69 (DBh) STATUS_ALL
    70. 7.70 (DDh) EXT_WRITE_PROTECTION
    71. 7.71 (DEh) IMON_CAL
    72. 7.72 (FCh) FUSION_ID0
    73. 7.73 (FDh) FUSION_ID1
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Inductor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 Compensation Selection
        5. 8.2.3.5 VCC and VRDV Bypass Capacitors
        6. 8.2.3.6 BOOT Capacitor Selection
        7. 8.2.3.7 VOSNS and GOSNS Capacitor Selection
        8. 8.2.3.8 PMBus Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on EVM
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.12 (21h) VOUT_COMMAND

CMD Address21h
Write Transaction:Write Word
Read Transaction:Read Word
Format:ULINEAR16 per (20h) VOUT_MODE
NVM Back-up:No (VBOOT_OFFSET_1) / VOUT_SCALE_LOOP
Updates:on-the-fly

The regulated output can be set by PMBus or by the result of pin-strapping on pin VSEL. When PMBus or pin-strapping is used to set the regulated voltage, the commanded output voltage in volts is determined by a combination of VOUT_COMMAND, VOUT_TRIM, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, and OPERATION commands, as below. As stated in the description of the VOUT_MODE command, the VOUT step size is 1.953mV.

This register can be changed during soft-start or soft-stop. However, the rail will continue to ramp up/down to the original target (VBOOT) at the rate programmed into TON_RISE/TOFF_FALL. After soft-start completes (and if VOUT_COMMAND is different from the VBOOT value), the device will immediately transition from the VBOOT value to the latest written VOUT_COMMAND at the programmed VOUT_TRANSITION_RATE. Writes to VOUT_COMMAND during soft-stop will be acknowledged, however, no transition will occur and VOUT_COMMAND will get automatically updated back to VBOOT at the conclusion of soft-stop. After soft-start has completed, writes to VOUT_COMMAND are also allowed even if the output voltage is still transitioning to a previously programmed VOUT_COMMAND. The output voltage will immediately begin transitioning to the newly programmed VOUT_COMMAND at the rate specified by VOUT_TRANSITION_RATE. The device does not wait for the prior transition to complete.

Return to Supported PMBus Commands.

Figure 7-19 (21h) VOUT_COMMAND Register Map
15141312111098
RRRR/WR/WR/WR/WR/W
VOUT_COMMAND (High Byte)
76543210
R/WR/WR/WR/WR/WR/WR/WR/W
VOUT_COMMAND (Low Byte)

The programmed Vout is computed as:

default*: XXX0 0000 0000 0000 (binary) (X means writes will be ignored and reads will be 0)

VOUT = (VOUT_COMMAND + VOUT_TRIM + (VOUT_MARGIN_HIGH – 1) * VOUT_COMMAND * OPERATION[5] – (1 – VOUT_MARGIN_LOW) * VOUT_COMMAND * OPERATION[4]) * VOUT_MODE

LEGEND: R/W = Read/Write; R = Read only
Table 7-6 Register Field Descriptions
BitFieldAccessResetDescription
15:13VOUT_COMMANDR000bNot used and always set to 0.
12:0VOUT_COMMANDR/WVBOOT_OFFSET_1 (see below)Sets the output voltage target via the PMBus interface.

VBOOT Voltage

At power up, the reset value of VOUT_COMMAND is derived from VBOOT_OFFSET_1 / VOUT_SCALE_LOOP . When the rail is disabled by the mechanism programmed to ON_OFF_CONFIG or due to a fault, the value in VOUT_COMMAND is updated to VBOOT.

When the PMB_ADDR/VORST# pin is configured as a RESET# pin in SYS_CONFIG_USER1 (EN_VORST), assertion of the PMB_ADDR/VORST# pin causes the output voltage to return to the VBOOT value in VBOOT_OFFSET_1 (VBOOT_1), and causes the VOUT_COMMAND value to be updated accordingly.

Data Validity

Writes to VOUT_COMMAND for which the resulting value, including any offset from VOUT_TRIM, is greater than the current (24h) VOUT_MAX or less than the current (2Bh) VOUT_MIN, causes the VOUT_COMMAND to move to the value specified by (2Bh) VOUT_MIN or (24h) VOUT_MAX respectively. The VOUT_MAX_MIN warning bit is set in STATUS_VOUT, which sets the appropriate bit in STATUS_WORD, and the host is notified per the PMBus 1.3.1 Part II specification, section 10.2.

The TPS546B26 can not produce output voltages greater than 0.75V / VOUT_SCALE_LOOP. If VOUT_COMMAND is set greater than this but lower than (24h) VOUT_MAX, the TPS546B26 will not trigger a MIN/MAX warning in Section 7.45