SLVSI23A September   2025  – December 2025 DRV81646

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface and Slew Rate (RSLEW/CNTL)
      2. 6.3.2 Current Sensing With FET Source Terminals
      3. 6.3.3 Integrated Clamp Diode, VCLAMP
      4. 6.3.4 Protection Circuits
        1. 6.3.4.1 ILIM Analog Current Limit
          1. 6.3.4.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.4.2 Cut-Off Delay (COD)
        3. 6.3.4.3 INRUSH Mode
        4. 6.3.4.4 Thermal Shutdown (TSD)
        5. 6.3.4.5 Undervoltage Lockout (UVLO)
      5. 6.3.5 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
      3. 6.4.3 SPI Mode
        1. 6.4.3.1 Parity Bit Calculation
        2. 6.4.3.2 SPI Input Packet
        3. 6.4.3.3 SPI Response Packet
        4. 6.4.3.4 SPI Error Reporting
        5. 6.4.3.5 SPI Daisy Chain
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.5 Fault Conditions Summary

Table 6-7 summarizes the fault conditions and how to recover from each condition. Additionally, the nFAULT pin is pulled low momentarily when the device first wakes up (VM > VUVLO(rising)). After time tnFAULT_VALID the nFAULT pin accurately reports any fault states, but during the tnFAULT_VALID time the microcontroller can ignore any nFAULT low signals.

Table 6-7 Fault Conditions Summary
FAULT SPI FAULT [X] – FAULT BIT OF CHANNEL X INRUSH COUNTER NFAULT PIN SDO IN TH_SCLK INTERVAL RECOVERY
Channel Overtemperature, TJ_CHx > TTSD 0 < t < tINRUSH Not set Paused High SDI TJ < (TTSD – TTSD_HYS)
t > tINRUSH Set only for affected channel - Pulled Low SDI
Global (Die) Overtemperature, TJ > TTSD 0 < t < tINRUSH Set for all channels Paused Pulled Low SDI TJ < (TTSD – TTSD_HYS)
t > tINRUSH —
COD time expiry, when COD enabled Set only for affected channel - Pulled Low SDI tRETRY elapses
SPI Error Not set - High Low Next valid SPI frame
VM Undervoltage (UVLO), VVM < VUVLO VM falling SPI unavailable — Internal circuits disabled SPI unavailable VVM > VUVLO VM rising