SLVSI23A September   2025  – December 2025 DRV81646

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface and Slew Rate (RSLEW/CNTL)
      2. 6.3.2 Current Sensing With FET Source Terminals
      3. 6.3.3 Integrated Clamp Diode, VCLAMP
      4. 6.3.4 Protection Circuits
        1. 6.3.4.1 ILIM Analog Current Limit
          1. 6.3.4.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.4.2 Cut-Off Delay (COD)
        3. 6.3.4.3 INRUSH Mode
        4. 6.3.4.4 Thermal Shutdown (TSD)
        5. 6.3.4.5 Undervoltage Lockout (UVLO)
      5. 6.3.5 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
      3. 6.4.3 SPI Mode
        1. 6.4.3.1 Parity Bit Calculation
        2. 6.4.3.2 SPI Input Packet
        3. 6.4.3.3 SPI Response Packet
        4. 6.4.3.4 SPI Error Reporting
        5. 6.4.3.5 SPI Daisy Chain
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.4.3 INRUSH Mode

The DRV81646 offers an INRUSH mode which boosts the current limit for a 10ms interval (tINRUSH) to support capacitive loads such as lamps which require a large current at turn on. To enable INRUSH mode, leave the COD/INRUSH pin unconnected or put a pulldown resistor larger than or equal to 1MΩ on the pin.

The current limit during tINRUSH is IINRUSH = 120 ÷ RILIM[kΩ] for RILIM≥ 40kΩ. This is also equal to 2 times the ILIM current limitation value. IINRUSH_ACTIVATE = IINRUSH + 50%, or

Equation 16. IINRUSH[A] = 120 × RILIM[kΩ]
Equation 17. IINRUSH_ACTIVATE[A] = IINRUSH × 1.50

For example, a 60kΩ resistor on the ILIM pin results in IINRUSH = 120 ÷ 60 = 2.0A. The inrush current regulation only activates after the current passes IINRUSH_ACTIVATE = 2.0A × 1.5 = 3.0A. After 10ms the current is regulated at the ILIM level. Figure 6-11 shows the inrush behavior followed by regular ILIM current regulation until thermal shutdown or until the current drops below the ILIM level.

DRV81646 Current Limit Value During INRUSH Figure 6-11 Current Limit Value During INRUSH

If a channel shuts off during tINRUSH due to thermal shutdown, the inrush timer is paused until the channel temperature falls to a safe level, below TTSD-TTSD_HYS. Then the timer continues with the boosted current limit IINRUSH. The inrush timer count is reset if the corresponding INx is pulled low. When INx is pulled high the inrush counter restarts. Figure 6-12 illustrates this timer functionality with a load that causes a thermal shutdown during tINRUSH, and the current regulation dropping down to the ILIM setting after t > tINRUSH.

During tINRUSH, the nFAULT pin and NFAULT SPI bit is masked for that channel to prevent unwanted fault trigger during the initial inrush period. The nFAULT pin and bit still reports a fault on a different channel. For example, if Channel 1 is within tINRUSH and Channel 3 has a thermal shutdown, the nFAULT pin and bit report a fault.

Table 6-6 INRUSH Mode Fault Reporting
DEVICE STATE CURRENT LIMIT nFAULT PIN FAULT BIT (SPI)
t < tINRUSH IINRUSH Masked during Inrush period tINRUSH The FAULT bit of the corresponding channel is masked during Inrush period tINRUSH .
t > tINRUSH ILIM Pulled low if a power stage hits thermal shutdown. Released when channel temperature returns to a safe level. The FAULT bit of the corresponding channel is set if channel hits thermal shutdown. The bit is cleared automatically at the end of valid SPI transaction
DRV81646 INRUSH Timer Example With Channel Thermal Shutdown During tINRUSH Figure 6-12 INRUSH Timer Example With Channel Thermal Shutdown During tINRUSH