SLVSI23A September   2025  – December 2025 DRV81646

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface and Slew Rate (RSLEW/CNTL)
      2. 6.3.2 Current Sensing With FET Source Terminals
      3. 6.3.3 Integrated Clamp Diode, VCLAMP
      4. 6.3.4 Protection Circuits
        1. 6.3.4.1 ILIM Analog Current Limit
          1. 6.3.4.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.4.2 Cut-Off Delay (COD)
        3. 6.3.4.3 INRUSH Mode
        4. 6.3.4.4 Thermal Shutdown (TSD)
        5. 6.3.4.5 Undervoltage Lockout (UVLO)
      5. 6.3.5 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
      3. 6.4.3 SPI Mode
        1. 6.4.3.1 Parity Bit Calculation
        2. 6.4.3.2 SPI Input Packet
        3. 6.4.3.3 SPI Response Packet
        4. 6.4.3.4 SPI Error Reporting
        5. 6.4.3.5 SPI Daisy Chain
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.4.1 Layout Guidelines

  • Place the bulk capacitor to minimize the distance of the high-current path through the motor driver device. Make the connecting metal trace widths as wide as possible, and numerous vias must be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
  • Use wide metal traces for the high-current device outputs.
  • The VM pins are bypassed to GND pins using low-ESR ceramic bypass capacitors with a recommended value rated for VM. The capacitors are placed as close to the VM pins as possible with a thick trace or ground plane connection to the device VNEG pins.
  • In general, inductance between the power supply pins and decoupling capacitors must be avoided.
  • The thermal PAD of the package must be connected to system ground.
    • Try to use a big unbroken single ground plane for the whole system / board. The ground plane can be made at bottom PCB layer. Figure 7-5 shows an example of temperature rise from constricted versus continuous ground pours underneath the driver.
    • To minimize the impedance and inductance, the traces from ground pins are as short and wide as possible, before connecting to bottom layer ground plane through vias.
    • Use multiple vias to reduce the impedance.
    • Try to clear the space around the device as much as possible especially at bottom PCB layer to improve the heat spreading.
    • Single or multiple internal ground planes connected to the thermal PAD also help spread the heat and reduce the thermal resistance.
  • For more layout guidelines and best practices see the Best Practices for Board Layout of Motor Drivers application note.
DRV81646 Broken Ground vs Continuous Ground Pour Heat Map Figure 7-5 Broken Ground vs Continuous Ground Pour Heat Map