SLVSI23A September   2025  – December 2025 DRV81646

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface and Slew Rate (RSLEW/CNTL)
      2. 6.3.2 Current Sensing With FET Source Terminals
      3. 6.3.3 Integrated Clamp Diode, VCLAMP
      4. 6.3.4 Protection Circuits
        1. 6.3.4.1 ILIM Analog Current Limit
          1. 6.3.4.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.4.2 Cut-Off Delay (COD)
        3. 6.3.4.3 INRUSH Mode
        4. 6.3.4.4 Thermal Shutdown (TSD)
        5. 6.3.4.5 Undervoltage Lockout (UVLO)
      5. 6.3.5 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
      3. 6.4.3 SPI Mode
        1. 6.4.3.1 Parity Bit Calculation
        2. 6.4.3.2 SPI Input Packet
        3. 6.4.3.3 SPI Response Packet
        4. 6.4.3.4 SPI Error Reporting
        5. 6.4.3.5 SPI Daisy Chain
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
Effect of Load Resistance on Power Dissipation Before TSD

The resistance of the load affects how long the channel operates in the linear region before hitting thermal shutdown. The resistance functions similarly to a linear drop-out regulator (LDO), where a higher voltage drop requires the device to dissipate more power.

For example, take a 24V system with a 1A ILIM setting for a 5Ω load versus an 11Ω load. Without current limiting these draw 4.8A and 2.2A respectively, but with the ILIM feature, these regulate to 1A. Use Equation 3 to calculate the linear region resistance of the FET to achieve this 1A current limit:

Equation 3. I=VR
Equation 4. I L I M = V V M R L O A D + R D S O N

Rearrange Equation 4 to solve for RDS(ON), then plug in the system values for loads 5Ω and 11Ω:

Equation 5. R D S O N = V V M I L I M - R L O A D
Equation 6. R D S O N _ 5 Ω = 24 V 1 A - 5 Ω R D S O N _ 5 Ω = 19 Ω
Equation 7. R D S O N _ 11 Ω = 24 V 1 A - 11 Ω R D S O N _ 11 Ω = 1 3 Ω

Use this resistance to calculate the power dissipated inside the DRV81646 FET:

Equation 8. P F E T _ 5 Ω = I 2 × R = 1 A 2 × 19 Ω = 19 W
Equation 9. P F E T _ 11 Ω = I 2 × R = 1 A 2 × 1 3 Ω = 1 3 W

As in Equation 8 and Equation 9, even though both loads are limited to 1A, the DRV81646 has to dissipate more power for a 5Ω load than an 11Ω load. This power dissipation directly correlates with the temperature rise of the FET over time. More power dissipated means the channel hits thermal shutdown faster.