SLVSI75 May 2026 DRV8218
ADVANCE INFORMATION
When the MODE pin is floating (Hi-Z), the device is in half-bridge control mode. This mode allows for each half-bridge to be directly controlled to support high-side slow decay (or brake), driving two independent loads, or paralleling the outputs for higher current capability for a single load. Table 7-5 shows the truth table for independent half-bridge mode. The Hi-Z state for the MODE pin can be implemented by setting the microcontroller GPIO pin as an Input for the MODE pin.
The half-bridge control mode does not support autosleep mode. One way to enter autosleep mode is to set the MODE, IN1, and IN2 pins to logic low, which puts the device into PWM mode and autosleep entry. Alternatively, the VCC pin can be supplied from a microcontroller GPIO pin where setting the GPIO pin low brings the device into undervoltage lockout (UVLO) condition with the outputs all Hi-Z. See Section 7.5.2 for more details.
To wake up the DRV8218 in half-bridge mode, bring VCC high, then set IN1 or IN2 high for longer than tWAKE before returning low or sending a PWM signal. Figure 8-18 and Figure 8-19 show this wake-up procedure.
| VCC | MODE | IN1 | IN2 | OUT1 | OUT2 | DESCRIPTION |
|---|---|---|---|---|---|---|
| 0V | X | X | X | Hi-Z | Hi-Z | Low-power sleep mode in UVLO |
| 1.8 - 5.5V | 0 | 0 | 0 | Hi-Z | Hi-Z | (Not Independent half-bridge mode) H-bridge disabled/low-power automatic sleep mode |
| 1.8 - 5.5V | Hi-Z | 0 | X | L | X | OUT1 low-side On |
| 1.8 - 5.5V | Hi-Z | 1 | X | H | X | OUT1 high-side On |
| 1.8 - 5.5V | Hi-Z | X | 0 | X | L | OUT2 low-side On |
| 1.8 - 5.5V | Hi-Z | X | 1 | X | H | OUT2 high-side On |