SLVSIA7 March   2025 TPSI3050M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Transmission of the Enable State
      2. 7.3.2  Power Transmission
      3. 7.3.3  Gate Driver
      4. 7.3.4  Modes Overview
      5. 7.3.5  Three-Wire Mode
      6. 7.3.6  Two-Wire Mode
      7. 7.3.7  VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 7.3.8  Keep-Off Circuitry
      9. 7.3.9  Power Supply and EN Sequencing
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 8.2.2.2 CDIV1, CDIV2 Capacitance
        3. 8.2.2.3 RPXFR Selection
        4. 8.2.2.4 CVDDP Capacitance
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Start-up Time and Recovery Time
        7. 8.2.2.7 Supplying Auxiliary Current, IAUX From VDDM
        8. 8.2.2.8 VDDM Ripple Voltage
      3. 8.2.3 Application Curves
      4. 8.2.4 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.5 Three-Wire Mode

Three-wire mode is used for applications that require higher levels of power transfer or the shortest propagation delay TPSI3050M can offer. VDDP is supplied independently from the EN pin by a low output impedance external supply that can deliver the required power. In this mode, power from the primary side to the secondary side always occurs regardless of the state of the EN pin. Setting the EN pin logic high or low asserts or de-asserts VDRV, thereby enabling or disabling the external switch, respectively. Figure 7-1 shows the basic setup required for three-wire mode operation which requires EN, VDDP, and VSSP signals. EN can be driven up to 5.5V which is normally driven from the circuitry residing on the same rail as VDDP. In this example, the TPSI3050M is being used to drive back-to-back MOSFETs in a common-source configuration. CVDDP provides the required decoupling capacitance for the VDDP supply rail of the device. CDIV1 and CDIV2 provide the required decoupling capacitances of the VDDH and VDDM supply rails that provide the peak current to drive the external MOSFETs.

Figure 7-2 shows the basic operation from start-up to steady-state conditions. Figure 7-2 shows operation using the TPSI3050M. After power up, the TPSI3050M begins to transfer power from VDDP to the secondary side for a fixed time period (25μs typical) at a duty cycle rate determined by RPXFR, which begins to charge up the VDDH (and VDDM) secondary side rails. Power transfer continues as long as VDDP is present. The time required to fully charge VDDH depends on several factors including the values of VDDP, CDIV1, CDIV2, RPXFR, and the overall power transfer efficiency. When the application drives the EN pin to a logic high, the TPSI3050M signals information from the primary side to the secondary side to assert VDRV and drive it high. Similarly, setting EN pin to a logic low causes VDRV to be driven low.

TPSI3050M Three-Wire Mode Simplified SchematicFigure 7-1 Three-Wire Mode Simplified Schematic
TPSI3050M Three-Wire Mode With TPSI3050MFigure 7-2 Three-Wire Mode With TPSI3050M

To reduce average power, the TPSI3050M transfers power from the primary side to the secondary side in a burst fashion. The period of the burst is fixed while the burst on time is programmable by selecting one of seven appropriate resistor values, RPXFR, from the PXFR to VSSP pins, thereby changing the duty cycle of the power converter. This action provides flexibility in the application, allowing tradeoffs in power consumed versus power delivered. Higher power converter settings increase the burst on time which, in turn, increases average power consumed from the VDDP supply and increases the amount of power transferred to the secondary side VDDH and VDDM supplies. Similarly, lower power converter settings decrease the burst on time which, in turn, decreases average power consumed from the VDDP supply and decreases the amount of power transferred to the secondary side.

Table 7-1 summarizes the three-wire mode power transfer selection.

Table 7-1 Three-Wire Mode Power Transfer Selection
RPXFR(1)(2)POWER CONVERTER DUTY CYCLE
(THREE-WIRE MODE, NOMINAL)		DESCRIPTION
7.32kΩ13.3%The device supports seven, fixed power transfer settings, by selection of a corresponding RPXFR value . Selecting a given power transfer setting adjusts the duty cycle of the power converter and hence the amount of power transferred. Higher power transfer settings leads to an increased duty cycle of the power converter leading to increased power transfer and consumption. During power up, the power transfer setting is determined and remains fixed at that setting until VDDP power cycles.
9.09kΩ26.7%
11kΩ40.0%
12.7kΩ53.3%
14.7kΩ66.7%
16.5kΩ80.0%
20kΩ93.3%
(1) Standard resistor (EIA E96), 1% tolerance, nominal value.
(2) RPXFR ≥ 100kΩ or RPXFR ≤ 1kΩ sets the duty cycle of the power converter to 13.3%.