SLVSIA7 March 2025 TPSI3050M
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| COMMON | ||||||
| VVDDP_UV_R | VDDP undervoltage threshold rising | VDDP rising | 2.50 | 2.70 | 2.90 | V |
| VVDDP_UV_F | VDDP undervoltage threshold falling | VDDP falling | 2.35 | 2.55 | 2.75 | V |
| VVDDP_UV_HYS | VDDP undervoltage threshold hysterisis | 75 | mV | |||
| TSD | Temperature shutdown | 173 | ℃ | |||
| TSDH | Temperature shutdown hysteresis | 32 | ℃ | |||
| VVDDH_UV_R | VDDH undervoltage threshold rising | VDDH rising. | 8.3 | 8.6 | 9.0 | V |
| VVDDH_UV_F | VDDH undervoltage threshold falling | VDDH falling. | 6.3 | 6.6 | 6.9 | V |
| VVDDH_UV_HYS | VDDH undervoltage threshold hysterisis |
2 | V | |||
| IQ_VDDH | Internal quiescent current of VDDH supply. | 36 | µA | |||
| RDSON_VDRV | Driver on resistance in low state | Force VVDDH = 10V, sink IVDRV = 50mA. |
1.7 | Ω | ||
| Driver on resistance in high state | Force VVDDH = 10V, source IVDRV = 50mA. |
2.5 | Ω | |||
| IVDRV_PEAK | VDRV peak output current during rise | VVDDH in steady state, transition EN from low to high, measure peak current. |
1.5 | A | ||
| VDRV peak output current during fall | VVDDH in steady state, transition EN from high to low, measure peak current. |
3 | A | |||
| CMTI | Common-mode transient immunity | |VCM| = 1000V | 100 | V/ns | ||
| TWO-WIRE MODE | ||||||
| VIH_EN | Minimum voltage on EN to be detected as a valid logic high | 6.5 | V | |||
| VIL_EN | Maximum voltage on EN to be detected as a valid logic low | 2.0 | V | |||
| IEN_START | Enable current at startup | EN = 0V → 6.5V | 27 | mA | ||
| IEN | Enable current steady state | EN = 6.5V, RPXFR = 7.32kΩ, RPXFR ≥100kΩ or RPXFR ≤1kΩ, VVDDH in steady state. |
1.9 | mA | ||
| EN = 6.5V, RPXFR = 20kΩ, VVDDH in steady state. |
6.8 | mA | ||||
| VVDDP_RIPPLE | VDDP output voltage ripple | EN = 6.5V, VVDDH in steady state. | 600 | mV | ||
| VVDDH | VDDH output voltage | EN = 6.5V, VVDDH in steady state. |
9.4 | 10.2 | 11 | V |
| VVDRV_H | VDRV output voltage driven high | EN = 6.5V, VVDDH in steady state, no DC loading. |
9.4 | 10.2 | 11 | V |
| VVDRV_L | VDRV output voltage driven low | EN = 6.5V → 0V, VVDDH in steady state, sink 10mA load. |
0.1 | V | ||
| VVDDM_IAUX | Average VDDM voltage when sourcing external current | EN = 6.5V, steady state. RPXFR = 7.32kΩ, RPXFR ≥ 100kΩ or RPXFR ≤ 1kΩ, CDIV1 = CDIV2 = 220nF, source 0.4mA from VDDM, measure VDDM voltage. |
4.6 | 5.5 | V | |
| EN = 6.5V, steady state. RPXFR = 20kΩ, CDIV1 = CDIV2 = 220nF, source 1.7mA from VDDM, measure VDDM voltage. |
4.6 | 5.5 | V | |||
| THREE-WIRE MODE | ||||||
| VIH_EN | Minimum voltage on EN to be detected as a valid logic high. VIH(min) = 0.7 × VVDDP |
VVDDP = 3V | 2.1 | V | ||
| VVDDP = 5.5V | 3.85 | V | ||||
| VIL_EN | Maximum voltage on EN to be detected as a valid logic low | VVDDP = 3V | 0.9 | V | ||
| VVDDP = 5.5V | 1.65 | V | ||||
| IVDDP | VDDP average current in steady state | EN = 3.3V, VVDDP = 3.3V, RPXFR = 7.32kΩ, RPXFR ≥ 100kΩ or RPXFR ≤ 1kΩ, VVDDH in steady state, measure IVDDP. |
3.1 | mA | ||
| EN = 3.3V, VVDDP = 3.3V, RPXFR = 20kΩ VVDDH in steady state, measure IVDDP. |
26 | |||||
| EN = 5V, VVDDP = 5V, RPXFR = 7.32kΩ, RPXFR ≥ 100kΩ or RPXFR ≤ 1kΩ, VVDDH in steady state, measure IVDDP. |
4.8 | mA | ||||
| EN = 5V, VVDDP = 5V, RPXFR = 20kΩ, VVDDH in steady state, measure IVDDP. |
37 | mA | ||||
| VVDDM_IAUX | Average VDDM voltage when sourcing external current | VVDDP = 3.3V, EN = 0V, steady state, RPXFR = 7.32kΩ, CDIV1 = CDIV2 = 220nF, source 0.4mA from VDDM, measure VVDDM. |
4.6 | 5.5 | V | |
| VVDDP =
5.0V, EN = 0V, steady state, RPXFR = 7.32kΩ, CDIV1 = CDIV2 = 220nF, source 1.0mA from VDDM, measure VVDDM. |
4.6 | 5.5 | V | |||
| VVDDP = 3.3V, EN = 0V, steady state, RPXFR =20kΩ, CDIV1 = CDIV2 = 220nF, source 5.5mA from VDDM, measure VVDDM. |
4.6 | 5.5 | V | |||
| VVDDP = 5.0V, EN = 0V, steady state, RPXFR = 20kΩ, CDIV1 = CDIV2 = 220nF, source 10mA from VDDM, measure VVDDM. |
4.6 | 5.5 | V | |||
| VVDDH | VDDH output voltage | VVDDP = 3.0V, EN = 3.0V, VVDDH in steady state. |
9.4 | 10.2 | 11 | V |
| VVDRV_H | VDRV output voltage driven high | VVDDP = 3.0V, EN = 3.0V, VVDDH in steady state, no DC loading. |
9.4 | 10.2 | 11 | V |
| VVDRV_L | VDRV output voltage driven low | VVDDP = 3.0V, EN = 0V, VVDDH in steady state, VDRV sinking 10mA. |
0.1 | V | ||