SLVSJC6 December   2025 TPS544B27W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Frequency and Mode
      2. 6.3.2 Setting the Output Voltage
      3. 6.3.3 DC Load Line
      4. 6.3.4 Fault Management
      5. 6.3.5 Current Sense and Positive Overcurrent Protection
      6. 6.3.6 Negative Overcurrent Limit
      7. 6.3.7 Zero-Crossing Detection
      8. 6.3.8 Overtemperature Protection
      9. 6.3.9 PMBus® Interface
        1. 6.3.9.1 Setting the PMBus® Address
        2. 6.3.9.2 SMBus Alert Response Address
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 DCM Light Load Operation
    5. 6.5 Programming
      1. 6.5.1 PMBus® Command NVM Defaults
  8. 7 Register Maps
    1. 7.1 PMBus® Transaction Types
    2. 7.2 Conventions for Documenting Block Commands
    3. 7.3 PMBus Commands
      1. 7.3.1  OPERATION (Address = 01h)
      2. 7.3.2  ON_OFF_CONFIG (Address = 02h)
      3. 7.3.3  CLEAR_FAULTS (Address = 03h)
      4.      42
      5. 7.3.4  PASSKEY (Address = 0Eh)
      6. 7.3.5  WRITE_PROTECT (Address = 10h)
      7. 7.3.6  STORE_USER_ALL (Address = 15h)
      8.      46
      9. 7.3.7  RESTORE_USER_ALL (Address = 16h)
      10.      48
      11. 7.3.8  CAPABILITY (Address = 19h)
      12. 7.3.9  SMBALERT_MASK (Address = 1Bh)
      13.      51
      14. 7.3.10 SMBALERT_MASK Registers
        1. 7.3.10.1  ALERT_MASK_BYTE (Address = 78h) [Reset = C8h]
        2. 7.3.10.2  ALERT_MASK_WORD (Address = 79h) [Reset = 0Dh]
        3. 7.3.10.3  ALERT_MASK_VOUT (Address = 7Ah) [Reset = XXh]
        4. 7.3.10.4  ALERT_MASK_IOUT (Address = 7Bh) [Reset = XFh]
        5. 7.3.10.5  ALERT_MASK_INPUT (Address = 7Ch) [Reset = XXh]
        6. 7.3.10.6  ALERT_MASK_TEMPERATURE (Address = 7Dh) [Reset = XFh]
        7. 7.3.10.7  ALERT_MASK_CML (Address = 7Eh) [Reset = XXh]
        8. 7.3.10.8  ALERT_MASK_OTHER (Address = 7Fh) [Reset = XFh]
        9. 7.3.10.9  ALERT_MASK_MFR_SPECIFIC (Address = 80h) [Reset = XXh]
        10. 7.3.10.10 ALERT_MASK_PULSE_CATCHER (Address = CEh) [Reset = FXh]
      15. 7.3.11 VOUT_MODE (Address = 20h)
      16. 7.3.12 VOUT_COMMAND (Address = 21h)
      17. 7.3.13 VOUT_TRIM (Address = 22h)
      18. 7.3.14 VOUT_MAX (Address = 24h)
      19.      67
      20. 7.3.15 VOUT_MARGIN_HIGH (Address = 25h)
      21.      69
      22. 7.3.16 VOUT_MARGIN_LOW (Address = 26h)
      23.      71
      24. 7.3.17 VOUT_TRANSITION_RATE (Address = 27h)
      25.      73
      26. 7.3.18 VOUT_DROOP (Address = 28h)
      27. 7.3.19 VOUT_SCALE_LOOP (Address = 29h)
      28.      76
      29. 7.3.20 FREQUENCY_SWITCH (Address = 33h)
      30.      78
      31. 7.3.21 VIN_ON (Address = 35h)
      32.      80
      33. 7.3.22 VIN_OFF (Address = 36h)
      34.      82
      35. 7.3.23 VOUT_OV_FAULT_LIMIT (Address = 40h)
      36.      84
      37. 7.3.24 VOUT_OV_FAULT_RESPONSE (Address = 41h)
      38. 7.3.25 VOUT_OV_WARN_LIMIT (Address = 42h)
      39.      87
      40. 7.3.26 VOUT_UV_WARN_LIMIT (Address = 43h)
      41.      89
      42. 7.3.27 VOUT_UV_FAULT_LIMIT (Address = 44h)
      43.      91
      44. 7.3.28 VOUT_UV_FAULT_RESPONSE (Address = 45h)
      45. 7.3.29 IOUT_OC_FAULT_LIMIT (Address = 46h)
      46.      94
      47. 7.3.30 IOUT_OC_FAULT_RESPONSE (Address = 47h)
      48. 7.3.31 IOUT_OC_WARN_LIMIT (Address = 4Ah)
      49. 7.3.32 OT_FAULT_LIMIT (Address = 4Fh)
      50.      98
      51. 7.3.33 OT_FAULT_RESPONSE (Address = 50h)
      52. 7.3.34 OT_WARN_LIMIT (Address = 51h)
      53.      101
      54. 7.3.35 VIN_OV_FAULT_LIMIT (Address = 55h)
      55.      103
      56. 7.3.36 TON_DELAY (Address = 60h)
      57.      105
      58. 7.3.37 TON_RISE (Address = 61h)
      59. 7.3.38 TOFF_DELAY (Address = 64h)
      60. 7.3.39 TOFF_FALL (Address = 65h)
      61. 7.3.40 PIN_OP_WARN_LIMIT (Address = 6Bh)
      62.      110
      63.      111
      64.      112
      65. 7.3.41 STATUS_BYTE (Address = 78h)
      66. 7.3.42 STATUS_WORD (Address = 79h)
      67. 7.3.43 STATUS_VOUT (Address = 7Ah)
      68. 7.3.44 STATUS_IOUT (Address = 7Bh)
      69. 7.3.45 STATUS_INPUT (Address = 7Ch)
      70. 7.3.46 STATUS_TEMPERATURE (Address = 7Dh)
      71. 7.3.47 STATUS_CML (Address = 7Eh)
      72. 7.3.48 STATUS_OTHER (Address = 7Fh)
      73. 7.3.49 STATUS_MFR_SPECIFIC (Address = 80h)
      74. 7.3.50 READ_VIN (Address = 88h)
      75. 7.3.51 READ_IIN (Address = 89h)
      76. 7.3.52 READ_VOUT (Address = 8Bh)
      77. 7.3.53 READ_IOUT (Address = 8Ch)
      78. 7.3.54 READ_TEMPERATURE_1 (Address = 8Dh)
      79. 7.3.55 READ_PIN (Address = 97h)
      80. 7.3.56 PMBUS_REVISION (Address = 98h)
      81. 7.3.57 MFR_ID (Address = 99h)
      82. 7.3.58 MFR_MODEL (Address = 9Ah)
      83.      131
      84. 7.3.59 MFR_REVISION (Address = 9Bh)
      85. 7.3.60 IC_DEVICE_ID (Address = ADh)
      86. 7.3.61 IC_DEVICE_REV (Address = AEh)
      87.      135
      88. 7.3.62 EXTENDED_WRITE_PROTECT (Address = C7h)
      89. 7.3.63 NVM_PATCH_SPACE (Address = CDh)
      90. 7.3.64 CLOUD_OPTIONS (Address = CFh)
      91. 7.3.65 SYS_CFG_USER1 (Address = D0h)
      92.      140
      93. 7.3.66 SVID_ADDR_CFG_USER (Address = D1h)
      94. 7.3.67 PMBUS_ADDR (Address = D2h)
      95. 7.3.68 IMON_CAL (Address = D4h)
      96. 7.3.69 COMP (Address = D5h)
      97.      145
      98. 7.3.70 VBOOT_DCLL (Address = D6h)
      99. 7.3.71 VBOOT_OFFSET_1 (Address = D7h)
      100. 7.3.72 IIN_CAL (Address = D8h)
      101. 7.3.73 SVID_IMAX (Address = DAh)
      102.      150
      103. 7.3.74 SVID_EXT_CAPABILITY_VIDOMAX (Address = DBh)
      104. 7.3.75 FUSION_ID0 (Address = FCh)
      105. 7.3.76 FUSION_ID1 (Address = FDh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VDRV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 I_IN_P and I_IN_M Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 PMBus® Address Resistor Selection
      4. 8.2.4 Application Curves
        1. 8.2.4.1 Thermal Performance
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.2 Setting the Output Voltage

The TPS544B27W includes a fully integrated, internal, precision feedback divider. Using both the selectable feedback divider and precision adjustable reference, output voltages up to 5.5V can be obtained. To set the output voltage, the appropriate internal feedback divider gain (VOSL) must be selected through the PMBus interface. The method the internal feedback divider is programmed set by the value in the VOUT_CTRL bits in the PMBus (D0h) SYS_CFG_USER1 command as follows.

  • VOUT_CTRL = 00b or 01b: The output voltage is controlled through SVID and the internal feedback divider gain can be programmed to be 0.5 or 0.25 by selecting between the supported PROTOCOL_ID in the PMBus (D1h) SVID_ADDR_CFG_USER command. The PMBus (29h) VOUT_SCALE_LOOP command is read only in this configuration and reflects the active feedback divider gain.
  • VOUT_CTRL = 10b: The output voltage is controlled through PMBus and the internal feedback divider can be programmed to divider gains 1, 0.5, 0.25, or 0.125 using the PMBus (29h) VOUT_SCALE_LOOP command.

The valid output voltage range when configured through SVID or PMBus depends upon the feedback divider ratio configured as shown in Table 6-1. Setting the output voltage near the low end of the range can negatively affect VOUT regulation accuracy while setting the output voltage above the recommended range can limit the actual output voltage achieved.

Note: The output must be disabled through the PMBus (02h) ON_OFF_CONFIG mechanism before changing PMBus VOUT_CTRL, (29h) VOUT_SCALE_LOOP and PROTOCOL_ID. VOUT_CTRL and PROTOCOL_ID can be updated while the output is enabled, but the output must be disabled for the change to take effect. The device NACKs attempts to change PMBus (29h) VOUT_SCALE_LOOP while the output is enabled.
Table 6-1 Valid Output Voltage Range
INTERNAL DIVIDER GAIN VOUT_CTRL SVID (05h) PROTOCOL_ID PMBus® (29h) VOUT_SCALE_LOOP VALID OUTPUT VOLTAGE RANGE(1)
1.0 10b only N/A 1.0 0.250V to 0.768V
0.5 All values 07h, 09h (5mV VID table)(2) 0.5(3) 0.250V to 1.536V
0.25 All values 04h, 0Ah (10mV VID table)(2) 0.25(3) 0.500V to 3.072V
0.125 10b only N/A 0.125 1.000V to 5.500V
(1) The valid output voltage range must consider any offset added through PMBus (22h) VOUT_TRIM or OFFSET_1 and margin through PMBus (25h) VOUT_MARGIN_HIGH or PMBus (26h) VOUT_MARGIN_LOW.
(2) The PROTOCOL_ID values are the values in the SVID register. PROTOCOL_ID in the PMBus (D1h) SVID_ADDR_CFG_USER command is a 2-bit field. Refer to the PROTOCOL_ID description in Section 7 on how to select between 5mV or 10mV VID tables, and between VR13 or VR14.
(3) PMBus (29h) VOUT_SCALE_LOOP is read only with VOUT_CTRL = 00b or 01b.

The initial boot up voltage (VBOOT) after the output is enabled is set by either VBOOT_0 in the PMBus (D6h) VBOOT_DCLL command or VBOOT_1 in the PMBus (D7h) VBOOT_OFFSET_1 command. VBOOT_0 or VBOOT_1 is selected by the PMB_ADDR resistor as described in Section 6.3.9.1. VBOOT sets the initial boot up reference DAC voltage (VDAC_BOOT) and the regulated output voltage is scaled up by the internal feed back divider gain. The possible VBOOT voltages for each VOSL are shown in Table 6-2.

Table 6-2 VBOOT Voltages
VBOOT_0 or VBOOT_1 VDAC_BOOT (V) VBOOT (V)
VOSL = 1 VOSL = 0.5 VOSL = 0.25 VOSL = 0.125
00000b 0(1) 0(1) 0(1) 0(1) 0(1)
00001b 0.3 0.3 0.6 1.2 2.4
00010b 0.3125 0.3125 0.625 1.25 2.5
00011b 0.325 0.325 0.65 1.3 2.6
00100b 0.3375 0.3375 0.675 1.35 2.7
00101b 0.35 0.35 0.7 1.4 2.8
00110b 0.3625 0.3625 0.725 1.45 2.9
00111b 0.375 0.375 0.75 1.5 3
01000b 0.3875 0.3875 0.775 1.55 3.1
01001b 0.4 0.4 0.8 1.6 3.2
01010b 0.4125 0.4125 0.825 1.65 3.3
01011b 0.425 0.425 0.85 1.7 3.4
01100b 0.4375 0.4375 0.875 1.75 3.5
01101b 0.45 0.45 0.9 1.8 3.6
01110b 0.4625 0.4625 0.925 1.85 3.7
01111b 0.475 0.475 0.95 1.9 3.8
10000b 0.4875 0.4875 0.975 1.95 3.9
10001b 0.5 0.5 1 2 4
10010b 0.5125 0.5125 1.025 2.05 4.1
10011b 0.525 0.525 1.05 2.1 4.2
10100b 0.5375 0.5375 1.075 2.15 4.3
10101b 0.55 0.55 1.1 2.2 4.4
10110b 0.5625 0.5625 1.125 2.25 4.5
10111b 0.575 0.575 1.15 2.3 4.6
11000b 0.5875 0.5875 1.175 2.35 4.7
11001b 0.6 0.6 1.2 2.4 4.8
11010b 0.625 0.625 1.25 2.5 5
11011b 0.65 0.65 1.3 2.6 5.2
11100b 0.675 0.675 1.35 2.7 5.4
11101b 0.7 0.7 1.4 2.8 5.5
11110b 0.725 0.725 1.45 2.9 5.5
11111b 0.75 0.75 1.5 3 5.5
(1) VBOOT = 0V results in booting up into the VID0 state.

An offset (VOFFSET) can be added to the output voltage through the PMBus (22h) VOUT_TRIM command or OFFSET_1 located in the PMBus (D7h) VBOOT_OFFSET_1 command. VOFFSET affects the output voltage at startup and after start-up. The VBOOT voltage including VOFFSET can be calculated with Equation 1. How VOFFSET is applied to the output voltage depends on VOUT_CTRL as follows.

  • VOUT_CTRL = 00b: Selection between PMBus (22h) VOUT_TRIM and OFFSET_1 is enabled and the VOFFSET used is selected by the PMB_ADDR resistor as described in Section 6.3.9.1. The register value in the PMBus (22h) VOUT_TRIM command or OFFSET_1 field are loaded directly to the SVID (33h) OFFSET register. As a result, the step size of the VOFFSET added follows the 5mV or 10mV SVID VID table selected through PROTOCOL_ID. The VOFFSET added through PMBus (22h) VOUT_TRIM does not follow the PMBus (20h) VOUT_MODE format.
  • VOUT_CTRL = 01b or 10b: VOFFSET can only be added through the PMBus (22h) VOUT_TRIM command and the offset follows the PMBus (20h) VOUT_MODE format.
Equation 1. V B O O T = V D A C _ B O O T V O U T _ S C A L E _ L O O P + V O F F S E T

Table 6-3 gives an example on how to set the VBOOT voltage to 1.110V for each VOUT_CTRL setting. This table assumes Option 0 is selected through the PMB_ADDR resistor.

Table 6-3 Setting the VBOOT Voltage Example
VOUT_CTRL INTERNAL DIVIDER GAIN VBOOT_0 FIELD VALUE PMBus® (22h) VOUT_TRIM COMMAND VALUE
COMMAND OR FIELD VALUE
00b PROTOCOL_ID in PMBus (D1h) SVID_ADDR_CFG_USER 10b (VR14, 5mV) 10101b 0002h
01b PROTOCOL_ID in PMBus (D1h) SVID_ADDR_CFG_USER 10b (VR14, 5mV) 10101b 000Ah
10b PMBus (29h) VOUT_SCALE_LOOP E804h 10101b 000Ah

After start-up, the output voltage can be programmed to a different voltage through either the SVID interface or the PMBus interface, depending upon the value of VOUT_CTRL. When the output is controlled through the SVID interface, the device follows the SVID VID table. When the output voltage is controlled through PMBus, the device follows the PMBus (20h) VOUT_MODE format. If the output is disabled then re-enabled, the output voltage ramps up to VBOOT programmed in the active VBOOT register.

Table 6-4 summarizes the methods possible to program the output voltage.

Table 6-4 VOUT Control Methods
VOUT_CTRL METHOD START-UP AFTER STERT-UP
VOUT VOFFSET VOUT VOFFSET
00b(1) SVID VBOOT_0 or VBOOT_1 PMBus (22h) VOUT_TRIM or OFFSET_1 SVID commands (such as SetVID and SetWP) SVID register (33h) OFFSET
01b(2) SVID+PMBus VBOOT_0 or VBOOT_1 PMBus (22h) VOUT_TRIM SVID commands (such as SetVID and SetWP) Cannot be changed after start-up
10b(3) PMBus VBOOT_0 or VBOOT_1 PMBus (22h) VOUT_TRIM PMBus (21h) VOUT_COMMAND PMBus (22h) VOUT_TRIM
(1) Writes to PMBus (21h) VOUT_COMMAND are allowed but do not affect the output voltage.
(2) Writes to PMBus (21h) VOUT_COMMAND and SVID (33h) OFFSET register are allowed but do not affect the output voltage.
(3) Writes through the SVID interface are allowed but do not affect the output voltage.

There is no minimum programming limit to the voltage that can be programmed through either the SVID interface or the PMBus interface. The maximum output voltage that can be programmed is limited by either SVID VIDO_MAX field (located in SVID registers 09h and 0Ah) or PMBus (24h) VOUT_MAX command depending on the value of VOUT_CTRL as follows.

  • VOUT_CTRL = 00b: The output voltage is programmed only through the SVID interface, so the output voltage plus offset is limited by the SVID VIDO_MAX field.
  • VOUT_CTRL = 01b: The output voltage programmed through the SVID interface (such as with SetVID or SetWP commands) are limited by SVID VIDO_MAX field. The offset programmed through PMBus (22h) VOUT_TRIM is not limited.
  • VOUT_CTRL = 10b: The output voltage is programmed only through the PMBus interface, so the output voltage plus offset is limited by PMBus (24h) VOUT_MAX command.