SLVSL52 September   2026 XTR100

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ESD Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Zero-Drift Clocking
      2. 7.1.2 Basic Functionality in Loop-Powered Transmitters
      3. 7.1.3 Current Consumption
      4. 7.1.4 System Error Estimation
    2. 7.2 Typical Applications
      1. 7.2.1 XTR100 4mA – 20mA Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 XTR100 4mA – 20mA Low Voltage Transmitter
      3. 7.2.3 XTR100 Precision Divider and Adder
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

ESD Protection

XTR1xx terminals, apart from INP and L–, are ESD protected with clamping diodes to the supplies V+ and V– as in Figure 6-4 .

XTR100 XTR100 Internal Protection Devices Figure 6-4 XTR100 Internal Protection Devices

The terminals INP and L– of XTR1xx have a special ESD protection devices to allow the terminals to swing beyond the supply rails V+, and V–. These special devices have low-leakage at low temperature, but exhibit relatively large leakage at high temperature and non-zero voltage on INP and L–.

The leakage of INP protection appears as an input bias current on INP and input offset current between INP and INN. This current only affects device accuracy if input source impedance is high. The worst-case leakage-induced voltage INP input error is V E r r ( V I N P ) = I L e a k a g e × R s o u r c e . As this leakage is negligible at room temperature, only consider this leakage as drift error when Rsource is more than 0.1% compared to RIN.

The leakage on L– is directly added to ILOOP. However, this higher temperature leakage represents only 1ppm/100°C error relative to the full-scale of 20mA, and can be ignored for all practical purposes.

Amplifier B of XTR120 does not have the special protection devices, and the terminals are protected only by typical clamping diodes to the supplies V+ and V–, as in Figure 6-5. The same is true for the INH input pin for both XTR102 and XTR120, which is protected by typical clamping didoes. During normal operation, the typical input bias current of the XTR1xx internal amplifier is 10pA.

XTR100 XTR120
          Internal Protection Devices Figure 6-5 XTR120 Internal Protection Devices

There are no anti-parallel diodes between the input pins (+IN and –IN); therefore, the differential input maximum voltage is limited only by diodes connected to the supply voltage pins. However, use caution in cases where the input differential voltage exceeds the nominal operating input differential voltage. When inputs are separated, the switching offset-cancellation path internal to the amplifier exceeds normal operating conditions and can potentially create long settling behavior upon return to normal operation.