SLVSL52 September   2026 XTR100

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ESD Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Zero-Drift Clocking
      2. 7.1.2 Basic Functionality in Loop-Powered Transmitters
      3. 7.1.3 Current Consumption
      4. 7.1.4 System Error Estimation
    2. 7.2 Typical Applications
      1. 7.2.1 XTR100 4mA – 20mA Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 XTR100 4mA – 20mA Low Voltage Transmitter
      3. 7.2.3 XTR100 Precision Divider and Adder
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.4.1 Layout Guidelines

Figure 7-8 shows an example layout of representing part of Figure 7-3 circuit schematic. In general, keep good layout practices. Keep traces short and, when possible, use a printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.

  • Place a 0.1µF power supply bypass capacitor close to the V+ pin.
  • Use a low-ESR ceramic bypass capacitor.
  • Shorten routes to INP and INN pins, and keep them away from noisy nodes, like supply line.
  • Keep R2 close to the L− pin, and provide low impedance path for R2 to the GND plane.
  • Keep XTR100 away from heat sources on board to avoid creating thermal gradients.

If the user wants to have XTR100 board layout compatible with 5-pins DBV op amp footprint, use the layout in Figure 7-9. Two extra resistors are added to the layout, one at the input and one between input and L−.

  • When using XTR100 put 0Ω at the input, and leave the R1 placeholder unpopulated.
  • When using an op amp with 5p DBV package, put R1 and RIN in the indicated placeholders. The op amp is not connected to L− in this case.