SLVSNG2 August   2026 DRV8378-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings AUTO
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Mode Timings
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
      1. 7.3.1 Output Stage
      2. 7.3.2 Device Interface Modes
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware Interface
      3. 7.3.3 Control Modes
        1. 7.3.3.1 3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD with RMODE or to GVDD)
        2. 7.3.3.2 6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
        3. 7.3.3.3 DRV8378G Control mode with External GVDD
      4. 7.3.4 GVDD Linear Voltage Regulator
      5. 7.3.5 Charge Pump
    4. 7.4  Slew Rate Control
    5. 7.5  Cross Conduction (Dead Time)
    6. 7.6  Propagation Delay
    7. 7.7  Pin Diagrams
      1. 7.7.1 Logic Level Input Pin (Internal Pulldown)
      2. 7.7.2 Logic Level Input Pin (Internal Pullup)
      3. 7.7.3 Open Drain Pin
      4. 7.7.4 Push Pull Pin
    8. 7.8  Current Sense Amplifiers
      1. 7.8.1 Current Sense Amplifier Operation (29-pin variant)
    9. 7.9  Active Demagnetization
      1. 7.9.1 Automatic Synchronous Rectification Mode (ASR Mode)
        1. 7.9.1.1 Automatic Synchronous Rectification in Commutation
        2. 7.9.1.2 Automatic Synchronous Rectification in PWM Mode
      2. 7.9.2 Automatic Asynchronous Rectification Mode (AAR Mode)
    10. 7.10 Cycle-by-Cycle Current Limit
      1. 7.10.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
    11. 7.11 Protections
      1. 7.11.1 Overcurrent Protection (OCP)
        1. 7.11.1.1 OCP Latched Shutdown (OCP_MODE = 00b)
        2. 7.11.1.2 OCP Automatic Retry (OCP_MODE = 01b)
        3. 7.11.1.3 OCP Disabled (OCP_MODE = 11b)
        4. 7.11.1.4 OCP Report Only (OCP_MODE = 10b)
      2. 7.11.2 VM Supply Undervoltage Lockout (RESET)
      3. 7.11.3 GVDD Undervoltage Lockout (GVDD_UV)
      4. 7.11.4 VCP Charge Pump Undervoltage Lockout (CPUV)
      5. 7.11.5 Over Voltage Protections (OV)
      6. 7.11.6 Thermal Warning (OTW)
      7. 7.11.7 Thermal Shutdown (OTS)
    12. 7.12 Device Functional Modes
      1. 7.12.1 Functional Modes
        1. 7.12.1.1 Sleep Mode
        2. 7.12.1.2 Operating Mode
        3. 7.12.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.12.2 DRVOFF functionality
    13. 7.13 SPI Communication
      1. 7.13.1 Programming
        1. 7.13.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 CONTROL Registers
    2. 8.2 STATUS Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Power Supply Recommendations
      1. 9.2.1 Bulk Capacitance
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
      3. 9.3.3 Thermal Considerations
        1. 9.3.3.1 Power Dissipation
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information

7.8.1 Current Sense Amplifier Operation (29-pin variant)

The SOx pin on the DRV8378-Q1 outputs an analog voltage proportional to current flowing in the low side FETs multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels which can be set by the GAIN pin (in hardware device variant) or the GAIN bits (in SPI device variant).

Figure 6-1 shows the internal architecture of the current sense amplifiers. The current sense is implemented with the sense FET on each low-side FET of the DRV8378-Q1 device. This current information is fed to the internal I/V converter, which generates the CSA output voltage on the SOX pin based on the voltage on VREF pin and the Gain setting. The CSA output voltage can be calculated as :

Equation 3. DRV8378-Q1
DRV8378-Q1 Integrated Current Sense AmplifierFigure 7-15 Integrated Current Sense Amplifier

Figure 7-16 and Figure 7-17 show the detail of the amplifier operational range. In bi-directional operation, the amplifier output for 0V input is set at VREF/2. Any change in the differential input results in a corresponding change in the output times the CSA_GAIN factor. The amplifier has a defined linear region in which the amplifier can maintain operation.

DRV8378-Q1 Bidirectional Current Sense OutputFigure 7-16 Bidirectional Current Sense Output
DRV8378-Q1 Bidirectional Current Sense RegionsFigure 7-17 Bidirectional Current Sense Regions
Note: Current flowing into the FET is taken as positive and flowing out of FET is taken as negative
Note: The current sense amplifier supports dynamic gain change. The GAIN is sampled in every 1ms through pin sensing in HW variant and any GAIN change through SPI write (in SPI variant). After receiving the GAIN change command, the new GAIN is applied to all the three current sense amplifiers on the next falling edge of any INLx signal.